Abstract: A solid-state imaging unit includes: a pixel section including a plurality of pixels each including a photoelectric conversion section, a charge-voltage conversion section, and a transfer transistor transferring charge accumulated in the photoelectric conversion section to the charge-voltage conversion section; and a storage section storing information about an optimum value of an intermediate voltage to be applied to a gate of the transfer transistor at time of an intermediate transfer operation when a signal charge accumulated in the photoelectric conversion section is divided to be read in a predetermined times of the intermediate transfer operations and a complete transfer operation.

Abstract: A solid-state imaging device includes: a pixel array including a plurality of pixels disposed in a matrix, the pixels including a charge holding section configured to hold a signal charge transferred from a photoelectric conversion section, and to include a capacitor section having a first capacitance value and an additional capacitor section for increasing the first capacitance value to be a second capacitance value; and to part of a reset transistor configured to reset a charge held by the charge holding section, a test-voltage power source configured to apply a test voltage having a voltage different from a drive voltage of the reset transistor.

Abstract: A solid-state imaging unit includes: a pixel section including a plurality of pixels each including a photoelectric conversion section, a charge-voltage conversion section, and a transfer transistor transferring charge accumulated in the photoelectric conversion section to the charge-voltage conversion section; and a storage section storing information about an optimum value of an intermediate voltage to be applied to a gate of the transfer transistor at time of an intermediate transfer operation when a signal charge accumulated in the photoelectric conversion section is divided to be read in a predetermined times of the intermediate transfer operations and a complete transfer operation.

Abstract: A solid-state imaging unit includes: a pixel section including a plurality of pixels each including a photoelectric conversion section, a charge-voltage conversion section, and a transfer transistor transferring charge accumulated in the photoelectric conversion section to the charge-voltage conversion section; and a storage section storing information about an optimum value of an intermediate voltage to be applied to a gate of the transfer transistor at time of an intermediate transfer operation when a signal charge accumulated in the photoelectric conversion section is divided to be read in a predetermined times of the intermediate transfer operations and a complete transfer operation.

Abstract: A solid-state imaging device includes: a device portion in which unit constituent elements, each of which includes a charge detection unit detecting a charge that is generated on the basis of changes in physical information and a transfer unit transferring a signal charge detected by the charge detection unit, are arranged in a predetermined direction; and a supplied voltage control portion capable of transferring a part of the charge detected by the charge detection unit through supplying of a control voltage for suppressing blooming to the transfer unit and capable of transferring the signal charge detected by the charge detection unit through supplying of a first control voltage that is different from the control voltage for suppressing the blooming to the transfer unit.

Abstract: A solid-state imaging device includes: a device portion in which unit constituent elements, each of which includes a charge detection unit detecting a charge that is generated on the basis of changes in physical information and a transfer unit transferring a signal charge detected by the charge detection unit, are arranged in a predetermined direction; and a supplied voltage control portion capable of transferring a part of the charge detected by the charge detection unit through supplying of a control voltage for suppressing blooming to the transfer unit and capable of transferring the signal charge detected by the charge detection unit through supplying of a first control voltage that is different from the control voltage for suppressing the blooming to the transfer unit.

Abstract: A pixel driving portion 102 can carry out first read drive with which a transfer element is turned OFF in accordance with a drive signal TG to output a signal at an output node, and second read drive with which the transfer element is turned ON in accordance with the drive signal TG to transfer signal charges to the output node, thereby outputting a signal at the output node. A pixel signal reading portion 103, 104 outputs a signal corresponding to a difference between the signal read out in accordance with the second read drive and the signal read out in accordance with the first read drive.

Abstract: A solid-state imaging unit includes: a pixel section including a plurality of pixels each including a photoelectric conversion section, a charge-voltage conversion section, and a transfer transistor transferring charge accumulated in the photoelectric conversion section to the charge-voltage conversion section; and a storage section storing information about an optimum value of an intermediate voltage to be applied to a gate of the transfer transistor at time of an intermediate transfer operation when a signal charge accumulated in the photoelectric conversion section is divided to be read in a predetermined times of the intermediate transfer operations and a complete transfer operation.

Abstract: A solid-state imaging device includes: a pixel array including a plurality of pixels disposed in a matrix, the pixels including a charge holding section configured to hold a signal charge transferred from a photoelectric conversion section, and to include a capacitor section having a first capacitance value and an additional capacitor section for increasing the first capacitance value to be a second capacitance value; and to part of a reset transistor configured to reset a charge held by the charge holding section, a test-voltage power source configured to apply a test voltage having a voltage different from a drive voltage of the reset transistor.

Abstract: A pixel driving portion 102 can carry out first read drive with which a transfer element is turned OFF in accordance with a drive signal TG to output a signal at an output node, and second read drive with which the transfer element is turned ON in accordance with the drive signal TG to transfer signal charges to the output node, thereby outputting a signal at the output node. A pixel signal reading portion 103, 104 outputs a signal corresponding to a difference between the signal read out in accordance with the second read drive and the signal read out in accordance with the first read drive.

Abstract: A pixel driving portion 102 can carry out first read drive with which a transfer element is turned OFF in accordance with a drive signal TG to output a signal at an output node, and second read drive with which the transfer element is turned ON in accordance with the drive signal TG to transfer signal charges to the output node, thereby outputting a signal at the output node. A pixel signal reading portion 103, 104 outputs a signal corresponding to a difference between the signal read out in accordance with the second read drive and the signal read out in accordance with the first read drive.

Abstract: A solid-state imaging device includes: a device portion in which unit constituent elements, each of which includes a charge detection unit detecting a charge that is generated on the basis of changes in physical information and a transfer unit transferring a signal charge detected by the charge detection unit, are arranged in a predetermined direction; and a supplied voltage control portion capable of transferring a part of the charge detected by the charge detection unit through supplying of a control voltage for suppressing blooming to the transfer unit and capable of transferring the signal charge detected by the charge detection unit through supplying of a first control voltage that is different from the control voltage for suppressing the blooming to the transfer unit.

Abstract: A pixel driving portion 102 can carry out first read drive with which a transfer element is turned OFF in accordance with a drive signal TG to output a signal at an output node, and second read drive with which the transfer element is turned ON in accordance with the drive signal TG to transfer signal charges to the output node, thereby outputting a signal at the output node. A pixel signal reading portion 103, 104 outputs a signal corresponding to a difference between the signal read out in accordance with the second read drive and the signal read out in accordance with the first read drive.

Abstract: A semiconductor memory device includes a smaller number of elements. A method for reading stored data within the semiconductor memory device suppresses the reduction in the static noise margin accompanying a voltage drop of a power supply voltage, and improves the degree of integration of the circuit.

Abstract: A method of reading stored data in a semiconductor memory device able to suppress the reduction in the static noise margin accompanying a voltage drop of a power supply voltage, and able to improve the degree of integration of the circuit, that is, a method of reading stored data of a semiconductor memory device which has a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and a first bit line and having a control terminal connected to a word line, and a fourth transistor having a pair of input/output terminals connected between th