Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.

Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.

Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract: According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing.

Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a storage configured to store therein data temporarily; a notifying module configured to notify a host of data transfer permission with a specified amount of data to be written in the storage; a transfer module configured to transfer data transferred from the host according to the data transfer permission to the storage, and to transfer the data stored in the storage to be written to the non-volatile memory; and a controller configured to inhibit notification of the data transfer permission by the notifying module until transfer of the data to the non-volatile memory by the transfer module is completed after an amount of data necessary to be written in the non-volatile memory is stored in the storage.

Abstract: A storage device includes a first storage unit that stores data read from a recording medium based on an instruction received from a processing device, and transmitting the data stored in the first storage unit to the processing device. The storage device also includes a second storage unit that stores the instruction received from the processing device; a counter that counts the number of pieces of data stored in the first storage unit; and a control unit that transmits the data stored in the first storage unit to the processing device based on a count value of the counter and, when the data read upon the instruction is stored in the first storage unit, writes identification information indicating that storing data has been completed in the second storage unit and, based on the identification information, transmits the data stored in the first storage unit to the processing device.

Abstract: An index determining unit determines that a current position in a disk medium corresponds to a true index when reaching a true index pattern of servo information recorded in the disk medium. The determination is used for reading predetermined servo information so as to perform a servo control operation of a disk reading/writing head. The disk medium has the true index pattern in a first portion of the disk medium and also untrue index patterns of servo information in a predetermined number of second portions in proximity to the first portion along a track direction. The true index pattern and the untrue index patterns form a predetermined sequence.

Abstract: An object of the present invention is to minimize an overhead attributable to internal control and to provide a CDR type disk unit in which even when a head moves over a zone boundary, a sector pulse indicating a destination sector can be generated reliably without waiting for an index pulse. The disk unit includes a processing unit; a sector pulse generation unit which generates a sector pulse according to a signal written in the servo information on medium surface; and a format control unit which starts the formatting control when said sector pulse is received after a activating command is received from said processing unit; a target sector detection unit which detects the instant when said head reaches the target sector. The sector pulse generation unit stops outputting the sector pulses to the format control unit from when the access operation starts until a target pulse is received from the target sector detection unit.