Abstract: An arithmetic processing apparatus includes a queue and control circuitry, and executes a plurality of instructions in parallel and sequentially from executable instructions. In the arithmetic processing apparatus, the queue stores the plurality of instructions, and the control circuitry holds an indicator indicating a pipeline that executes a producer instruction included in the plurality of instructions and an execution stage of the producer instruction in the pipeline, executes data dependency resolution between the producer instruction and a consumer instruction that uses an execution result of the producer instruction and that is included in the plurality of instructions, and controls issuing timings of the plurality of instructions.

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

Abstract: A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

Abstract: A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.