Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

Abstract: A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

Abstract: A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.

Abstract: A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.

Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.

Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.

Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.

Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.