Abstract: A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory.

Abstract: A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.