Abstract: A sink circuit for protecting connectivity of a digital multimedia interface, the sink circuit is connected in a sink multimedia device. The sink circuit comprises a sink port configured to provide a connection to a source multimedia device; a termination coupled to the sink port; and a protection component coupled in series between the termination and a power source of the sink multimedia device, the protection component blocks any direct current path through the sink port when the sink multimedia device is off and the power source of the source multimedia device is on.

Abstract: An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N?1 comparators for comparing an input data stream to N?1 configurable thresholds, the input data stream is N-PAM modulated and the N?1 configurable thresholds are N?1 different voltage levels; a number of N?1 of edge detectors respectively connected to the N?1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

Abstract: A sink circuit for protecting connectivity of a digital multimedia interface, the sink circuit is connected in a sink multimedia device. The sink circuit comprises a sink port configured to provide a connection to a source multimedia device; a termination coupled to the sink port; and a protection component coupled in series between the termination and a power source of the sink multimedia device, the protection component blocks any direct current path through the sink port when the sink multimedia device is off and the power source of the source multimedia device is on.

Abstract: A Fast Ethernet and HDMI Ethernet channel (HEC) physical layer circuit. The physical layer circuit comprises a Fast Ethernet physical layer module implementing a physical layer specification of a Fast Ethernet communication standard; a hybrid circuit connected to the fast Ethernet physical layer module using a first twisted-pair wire and a second twisted-pair wire and capable of processing transmit and receive HDMI Ethernet channel (HEC) signals concurrently transported over a third twisted-pair wire; a switch for bypassing the hybrid circuit; and a controller for controlling the operation the hybrid circuit and the switch according to the operating mode of the physical layer circuit, wherein the operation mode of the physical layer circuit is any of a fast Ethernet and a HEC.

Abstract: An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication.

Abstract: An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication.

Abstract: An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N?1 comparators for comparing an input data stream to N?1 configurable thresholds, the input data stream is N-PAM modulated and the N?1 configurable thresholds are N?1 different voltage levels; a number of N?1 of edge detectors respectively connected to the N?1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

Abstract: A Fast Ethernet and HDMI Ethernet channel (HEC) physical layer circuit. The physical layer circuit comprises a Fast Ethernet physical layer module implementing a physical layer specification of a Fast Ethernet communication standard; a hybrid circuit connected to the fast Ethernet physical layer module using a first twisted-pair wire and a second twisted-pair wire and capable of processing transmit and receive HDMI Ethernet channel (HEC) signals concurrently transported over a third twisted-pair wire; a switch for bypassing the hybrid circuit; and a controller for controlling the operation the hybrid circuit and the switch according to the operating mode of the physical layer circuit, wherein the operation mode of the physical layer circuit is any of a fast Ethernet and a HEC.