Abstract: A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts.

Abstract: A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts.

Abstract: A method is described for eliminating overerasure in a nonvolatile memory that includes a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source. The nonvolatile memory is electrically erased until each of the plurality of memory cells has a threshold voltage below a predetermined erased voltage state. The nonvolatile memory then undergoes an equalization programming operation by applying an equalization programming voltage to the control gate of each of the plurality of memory cells such that the threshold voltage of each of the plurality of memory cells is saturated to the predetermined erased voltage state. The equalization programming voltage determines the predetermined erased voltage state. An apparatus for eliminating overerasure in the nonvolatile memory during erasing is also described.

Abstract: A method is described for eliminating overerasure in a nonvolatile memory that includes a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source. The nonvolatile memory is electrically erased until each of the plurality of memory cells has a threshold voltage below a predetermined erased voltage state. The nonvolatile memory then undergoes an equalization programming operation by applying an equalization programming voltage to the control gate of each of the plurality of memory cells such that the threshold voltage of each of the plurality of memory cells is saturated to the predetermined erased voltage state. The equalization programming voltage determines the predetermined erased voltage state. An apparatus for eliminating overerasure in the nonvolatile memory during erasing is also described.

Abstract: A process for making an integrated structure comprised of complementary MOS devices is described, where electrical isolation is provided by recessed field oxide regions and by field isolation implant regions. Starting with a single conductivity type semiconductor layer, such as P- type silicon, a first masking step is used to produce an N- type well therein. After this, a layer of silicon or silicide is formed through the same mask. In a second masking step, openings are made for the field isolation implant regions. The edge of the silicon or silicide layer determines the edge of the field isolation implant, which is therefore self-aligned to the edge of the well. This same mask is later used to determine the locations of the recessed oxide isolation regions. Subsequent masking steps are used to form polysilicon gate electrodes, source and drain regions of the active devices, contact holes and contact metal and interconnects.