Abstract: Methods and systems to generate a digital error indication of an input signal relative to a reference signal, using resistors, comparators, and latches. The digital error indication may indicate that the input signal is within a range of the reference signal, above the range, or below the range. The methods and systems may be implemented within a multi-phase digital voltage regulator to generate a digital error indication for each of a plurality of phase currents relative to an instantaneous average of the phase currents. The digital voltage regulator may be fabricated on an integrated circuit die with a corresponding load, such as a processor. The digital voltage regulator may include a plurality of multiplier or look-up based gain modules, each to receive a corresponding one of the digital error signals and to output one of three values. Outputs of each gain module may be integrated over time.

Abstract: Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed.

Abstract: Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed.

Abstract: Methods and systems to generate a digital error indication of an input signal relative to a reference signal, using resistors, comparators, and latches. The digital error indication may indicate that the input signal is within a range of the reference signal, above the range, or below the range. The methods and systems may be implemented within a multi-phase digital voltage regulator to generate a digital error indication for each of a plurality of phase currents relative to an instantaneous average of the phase currents. The digital voltage regulator may be fabricated on an integrated circuit die with a corresponding load, such as a processor. The digital voltage regulator may include a plurality of multiplier or look-up based gain modules, each to receive a corresponding one of the digital error signals and to output one of three values. Outputs of each gain module may be integrated over time.

Abstract: An apparatus and method for controlling the AGC in a receiver is described. Samples of the input signal are compared to the upper and lower threshold values which are defined by the dynamic range of the A-to-D converter. These samples are recorded and used in determining whether to count-up or count-down in counters prior to the time the signal is detected. These counts provide, in effect, a history of what has occurred prior to signal detection and are used in computing an AGC gain. The gain can be computed more quickly since there is zero latency in starting the calculation for correcting the AGC.

Abstract: An apparatus and method for controlling the AGC in a receiver is described. Samples of the input signal are compared to the upper and lower threshold values which are defined by the dynamic range of the A-to-D converter. These samples are recorded and used in determining whether to count-up or count-down in counters prior to the time the signal is detected. These counts provide, in effect, a history of what has occurred prior to signal detection and are used in computing an AGC gain. The gain can be computed more quickly since there is zero latency in starting the calculation for correcting the AGC.

Abstract: The present invention is directed to a method and apparatus for managing data flow between a serial bus device which operates at a first data rate and a parallel port device which operates at a second data rate. A serial bus receiver receives data from the serial bus device at the first data rate. A buffer unit is coupled to the serial bus receiver and the parallel port device. The buffer unit stores the received data at the first data rate and transfers the stored data to the parallel port device at the second data rate.

Abstract: The present invention is directed to a method and apparatus for converting between serial bus cycles and parallel port commands. A serial bus processor processes a serial bus transaction which is represented by the serial bus cycles and is responsive to the parallel port commands. A state machine circuit is coupled to the serial bus processor to provide a plurality of states corresponding to the serial bus transaction. The state machine circuit transitions from one of the states to any one of the states in response to a change condition asserted by a state signal.

Abstract: The present invention is a method and apparatus for virtualizing a serial bus information source/sink point of a serial bus device into an address space of a processor. A register unit is coupled to a parallel port device to support a serial bus transaction between the processor and the serial bus device. The register unit has a plurality of registers which are mapped into the address space of the processor via the parallel port device. One of the plurality of registers corresponding to the serial bus information source/sink point. A control circuit is coupled to the register unit to allow the processor to access the information source/sink point via the parallel port device.