Abstract: An overcurrent protection system and method are disclosed. In one embodiment the overcurrent protection system includes a first switch connected between a supply voltage and an output voltage. A comparator circuit provides a comparator output signal having first and second values that depend on a comparison of the output voltage relative to the supply voltage, the first value indicating an overcurrent condition. A control circuit is coupled to provide a control signal to a control node of the first switch for controlling the first switch in one of first and second operating modes according to the value of the comparator output signal. The control circuit controls the first switch in the first mode to limit the current through the first switch to a level between predetermined upper and lower current levels in response to the comparator output signal having the first value.

Abstract: An overcurrent protection system and method are disclosed. In one embodiment the overcurrent protection system includes a first switch connected between a supply voltage and an output voltage. A comparator circuit provides a comparator output signal having first and second values that depend on a comparison of the output voltage relative to the supply voltage, the first value indicating an overcurrent condition. A control circuit is coupled to provide a control signal to a control node of the first switch for controlling the first switch in one of first and second operating modes according to the value of the comparator output signal. The control circuit controls the first switch in the first mode to limit the current through the first switch to a level between predetermined upper and lower current levels in response to the comparator output signal having the first value.

Abstract: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with the present invention includes a first and second inverter coupled in series between an input node and an output node. A third inverter connects between the output node and a fourth inverter. A first circuit portion that establishes the low-to-high switching point connects between the fourth inverter and the first inverter. A second circuit portion connects between the fourth and first inverter that will block the switching current from draining the voltage supply after the transition from low-to-high has occurred.

Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Abstract: A low power input with hysteresis circuit provides input hysteresis (for instance, from supply voltage ranges of 0.8 volt to 5.5 volts), while reducing the high-current region and the overall power consumption of an electronic device. The present invention utiliizes resistors and feedback transistors to limit the “through current” of the device when it is switching, and to provide extra hysteresis to the input circuit. The hysteresis can be adjusted by altering the resistance of the resistors. The present invention provides a very large hysteresis, or may be slightly modified to supply very little hystersis while having little effect on propagation delays, as compared with conventional input circuits with similar hysteresis. Accordingly, the present invention reduces the high-current region and the power consumption of the device while providing the required hystersis on the input.

Abstract: The edge rate controller circuit includes: a first transistor coupled to an output control node; a second transistor coupled to the output control node; an edge rate control driver; a third transistor coupled to the first transistor; a fourth transistor coupled in parallel with the third transistor, the fourth transistor having a control node coupled to the edge rate control driver; a fifth transistor coupled to the second transistor; and a sixth transistor coupled in parallel with the fifth transistor, the sixth transistor having a control node coupled to the edge rate control driver.

Abstract: A bus-hold circuit includes an inverter (10) having an input (4) and an output (16). A first transistor (22) has a gate coupled to the output (16). A second transistor (20) has a source-drain current pat coupled in series with the current path of the first transistor (22) between a power supply terminal and a reference terminal. A third transistor (28) has a source-drain current path coupled between the gates of the first and second transistors (22, 20) and a gate coupled to the power supply terminal. A fourth transistor (30) has a source-drain current coupled between the gate of the second transistor (20) and the input and a gate coupled to the power supply terminal. A resistor (26) has a first terminal coupled to the source-drain current pats of the first and second transistors (22, 20) and a second terminal coupled to the input. The bush old circuit eliminates the need for a Schottky diode and allows near rail-to-rail bus operation.