Abstract: Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Abstract: An apparatus is described. The apparatus includes a first riser card connected to a first card. The apparatus also includes a second riser card connected to a second card, wherein, the first card's connection to the first riser card and the second card's connection to the second riser card pass through a vertical plane runs parallel to respective surfaces of the first and second riser cards.

Abstract: An apparatus is described. The apparatus includes a first riser card connected to a first card. The apparatus also includes a second riser card connected to a second card, wherein, the first card's connection to the first riser card and the second card's connection to the second riser card pass through a vertical plane runs parallel to respective surfaces of the first and second riser cards.

Abstract: Computer chassis with parallel backplanes are disclosed that include a first backplane with a first surface that can receive a first computing node. The computer chassis may further include a second backplane with a second surface that can receive a second computing node, and may include a chassis that encloses the first backplane, second backplane, first computing node, and second computing node. The first backplane and second backplane may be substantially parallel to each other, with the first surface facing the second surface. Other may be described and/or claimed.

Abstract: Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Abstract: Devices and methods include a component module configured for installation into a server. The component module includes a frame configured for installation in an installation direction. A component platform is movably coupled to the frame and movable between interfaced and decoupled positions. In one example, a component actuator arm extends between first and second actuator ends. A hinge rotatably couples the component actuator arm to the frame and is remote from the first actuator end, and the component actuator arm is rotatably coupled to the component platform at a joint, wherein the component actuator arm is movable between a decoupled configuration and an interfaced configuration. In the decoupled configuration, the component platform is in the decoupled position and recessed relative to the interfaced position.

Abstract: A system module is provided for coupling a switch fabric network to I/O resources such as a first disk system and a second disk system. The system module may include a first serverlet, a second serverlet and a first switching device coupled to each of the first serverlet and the second serverlet and to each of the I/O resources such that the first serverlet and the second serverlet share the I/O resources.

Abstract: Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are "Owned" and "Unowned." The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Abstract: A symmetric multiprocessor system constructed from industry standard commodity components together with an advanced dual-ported memory controller. The multiprocessor system comprises a processor bus; up to four Intel Pentium.RTM. Pro processors connected to the processor bus; an I/O bus; a system memory; and a dual-ported memory controller connected to the system memory, the dual ported memory controller having a first port connected to the processor bus to manage processor to system memory transactions and a second port connected to the I/O bus to manage I/O transactions. Furthermore, two such systems can be connected together through a common I/O bus, thereby creating an eight-processor Pentium.RTM. Pro processor SMP system.

Abstract: An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories.

Abstract: A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time.

Abstract: An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories.

Abstract: A dual AC input module providing AC line isolation of different phases without the use of relay control. Power supply load is supported through two AC line feeds, each feed being connected through a bridge rectifier to a common bulk DC power supply backplane. The parallel configuration of AC line feeds and bridge rectifiers eliminates the need for relay control logic to open relays and isolate a failed primary AC line feed prior to closing relays to connect a second AC feed to the power supply, as required with previous dual AC input module designs to isolate different line feeds of different phases.

Abstract: An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

Abstract: A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource.

Abstract: Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Abstract: In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit.

Abstract: In a computer, when a block of data is written to memory, it is common to attach a control word to the data. The control word is placed at a pre-arranged location, generally separate from the data. The control word contains important information about the data, such as starting address, length, etc. The presence of the control word indicates that the data is valid.Sometimes, for various reasons, the control word is written before all the data is written. This premature availability of the control word gives false information: the data is not yet completely written, yet the presence of the control word indicates otherwise. The invention prevents such a problem by preventing premature writing of the control word.