Abstract: A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability.

Abstract: A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb--Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.

Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.

Abstract: A multi-layer module that has incorporated therein an additional sheet with a heat generating film resistor formed thereon. A temperature responsive controller regulates the film resistor current in order to regulate the temperature at the surface of the module. The invention is applicable to both single chip and multiple chip modules, and for multi-chip modules a plurality of discrete film resistors on a single may be used.

Abstract: An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.

Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

Abstract: A low cost Surface Mount Carrier (SMC) for carrying integrated circuit chips mounted thereon. The carrier, or interposer, is a thin-small single layer or, a multi-layer deck of printed circuit board (FR-4) material with at least one direct chip attach (DCA) site for mounting a semiconductor chip. The DCA site has chip bonding pads wherein the integrated circuit chip's pads are wire bonded to or soldered to the carrier. The bonding pads are connected to wiring pads through interlevel vias and wiring lands or traces which may be on one of several wiring planes. The carrier is connected to the next level of packaging through the wiring pads.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path.

Abstract: A circuit includes a set of seven NPN transistors, a Schottky diode, and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor in the input circuit to the base of the lower output transistor, which is connected with its collector emitter connections in parallel with the emitter resistor of the input transistors which receive the input signals to the circuit. Two transistors are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section.

Abstract: A voltage regulator for regulating the voltage at a first node, comprisinga first voltage supply;a first node;a first transistor with a control terminal connected to the first node;a circuit for varying the VBE voltage drop of the first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from the first transistor; anda circuit for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.

Abstract: An apparatus for inclusion into a gate which provides that gate with an increased input noise margin while advantageously eliminating the need to operate that gate at an increased power supply potential.

Abstract: The logic circuit disclosed exhibits push-pull output characteristic by employing a saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.

Abstract: A small signal swing line driver, that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver includes a clamp connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver. The driver also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver and thereafter coupled onto quiet lines.

Abstract: Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

Abstract: A driver circuit to limit the di/dt downgoing transition to a desired value employs an active feedback path. The driver circuit utilizes a Schottky Barrier Diode as a current bleed to limit the base current of the drive circuit transistor. The active feedback path includes a normally conductive transistor which turns off when the output falls to a predetermined level. Elimination of the active feedback path in this condition insures maximum DC drive.

Abstract: Dotting capability is provided in a push/pull active collector type circuit by providing a clamping circuit to limit the current through the pull-up transistor and prevent current flow through that transistor when the output is pulled down via another driver.