Abstract: A system and method for cell charging and cell charge redistribution for a plurality of series connected rechargeable electrical energy storage cells where the objective of charging and redistribution of charge for individual cells is based on the optimization criteria of equalization of remaining coulombmetric capacity for all cells.

Abstract: State of health processes and systems are provided for analyzing a capacitor, such as a supercapacitor. The process includes, for instance: determining a measured capacitance of a capacitor; estimating an effective series resistance (ESR) of the capacitor; determining, using the measured capacitance and the effective series resistance, a linearized capacitance parameter (CAP) for the capacitor; and signaling should the CAP drop below, or the ESR rise above, a respective specified threshold for the capacitor. Using the CAP and the effective series resistance, an amount of energy remaining in the capacitor may be determined, upon which to base one or more actions.

Abstract: A system and method for cell charging and cell charge redistribution for a plurality of series connected rechargeable electrical energy storage cells where the objective of charging and redistribution of charge for individual cells is based on the optimization criteria of equalization of remaining coulombmetric capacity for all cells.

Abstract: A battery monitoring/control device includes a monitor/control device (35) that is operable to be integrated with a microprocessor system. The system includes a CPU (12) that interfaces with a data bus (14) and an address bus (16). The CPU (12) interfaces through a data line (40) with the control/monitor device (35) and control lines (28) and (34). Commands and data can be input to the control/monitor circuit (35) and data received therefrom. The control/monitor device (35) includes a controller/data register block (36) and a battery charge control/monitor block (44). The device (35) is operable to monitor the battery voltage of a secondary battery (46) during charging thereof and to control the rate of charge through a transistor (66). The battery monitor (90) determines when the voltage on the battery (46) reaches a predetermined level indicating full-charge.

Abstract: A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42).

Abstract: A three-state input circuit operable to sense three separate logic states on an input pad (10) is operable to sense whether the current is sourced to the pad from a positive source or sinked from the pad to a negative source to provide two logic states. A third logic state is provided when it is determined that current is not being sourced to or sinked from the pad (10). A current source (36) is connected from a positive rail (14) through the source/drain path of an N-channel transistor (40) to the pad (10). This provides a sink current comparator function. A source current comparator function is provided by a current source (42) that is connected to the pad (10) through the source/drain path of a P-channel transistor (46) and to a negative voltage rail (18). The transistor (40) has a first bias voltage V.sub.B1 connected to the gate thereof and the transistor (46) has a second bias voltage V.sub.B2 connected to the gate thereof.