Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.

Abstract: A data storage system configured for efficient mirroring of data between paired redundant controllers is provided. More particularly, in response to the receipt of customer data from a host for storage, a first controller segments the received customer data into one or more frames of data. In addition, the first controller determines or associates certain metadata for each frame of customer data, and inserts that metadata in the corresponding frame. The frames, including the metadata, are provided to a secondary controller. The secondary controller stores the customer data from a received frame in memory, and stores the corresponding metadata in another location of memory that is indexed to the location where the customer data was stored. The secondary controller may also associate a count value with each frame of data in order to distinguish the most recent frame of data should frames in memory have matching metadata.

Abstract: A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.

Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain metadata therefrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract: A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: A data storage system configured for efficient mirroring of data between paired redundant controllers is provided. More particularly, in response to the receipt of customer data from a host for storage, a first controller segments the received customer data into one or more frames of data. In addition, the first controller determines or associates certain metadata for each frame of customer data, and inserts that metadata in the corresponding frame. The frames, including the metadata, are provided to a secondary controller. The secondary controller stores the customer data from a received frame in memory, and stores the corresponding metadata in another location of memory that is indexed to the location where the customer data was stored. The secondary controller may also associate a count value with each frame of data in order to distinguish the most recent frame of data should frames in memory have matching metadata.

Abstract: A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

Abstract: A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.

Abstract: A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.

Abstract: A method and system for transferring a transport stream, such as from a satellite receiver to a networked computer system, are provided. The transport stream is parsed to derive multiple elementary streams including associated program identifiers, which are used to determine corresponding transfer locations in a host memory. Direct memory access transfers of the multiple elementary streams are then performed to the corresponding transfer locations in the host memory.

Abstract: A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

Abstract: A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain medtdata therfrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract: A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.

Abstract: A multiple client memory arbitration system supporting simultaneous arbitration access to a local cache memory and a remote cache memory for mirrored write operations to both the local cache memory and the remote cache memory by one of a local arbitration device or a remote cache memory at a time. The enhanced arbitration system includes active/active failover control by a surviving one of the local arbitration device or the remote arbitration device that have participated in the mirrored write operations between the respective local cache memory and the remote cache memory.