Abstract: Fluorescent reporter compounds having a chain terminating (thio)triphosphate nucleotide derivative, a fluorescent dye, and a linker of sufficient length to connect the nucleotide derivative to the fluorescent dye are provided. The fluorescent reporter compounds are used in DNA sequencing reactions and are substantially inactive toward exonuclease digestion.

Abstract: Fluorescent labeled reporter compounds having a modified cyanine dye that is coupled to a nucleotide derivative through a linker are disclosed. The compounds are useful for nucleic acid sequence analysis. The fluorescent labeled reporter compounds are ring-locked cyanine dyes that are coupled to a nucleotide derivative, such as a modified DNA base, through a linker. These fluorescent labeled reporter compounds can be used as DNA chain-terminators in DNA synthesis to generate DNA fragments that are fluorescently-labeled at the 3?-terminal end of the DNA fragment.

Abstract: A processor comprises a cache, a first TLB, and a tag circuit. The cache comprises a data memory storing a plurality of cache lines and a tag memory storing a plurality of tags. Each of the tags corresponds to a respective one of the cache lines. The first TLB stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB. The tag circuit is configured to identify one or more of the plurality of cache lines that are stored in the cache and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB and a hit by the first virtual address in the tag circuit, the tag circuit is configured to prevent a read of the tag memory in the cache.

Abstract: A way predictor comprises a decoder, a memory coupled to the decoder, and a circuit. The decoder is configured to decode an indication of a first address that is to access a cache, and is configured to select a set responsive to the indication of the first address. The memory is configured to output a plurality of values from a set of storage locations in response to the decoder selecting the set, wherein each of the plurality of values corresponds to a different way of the cache. Coupled to receive the plurality of values and a first value corresponding to the first address, the circuit is configured to generate a way prediction for the cache responsive to the plurality of values and the first value.

Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Abstract: The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not checked with the first instruction's destination. Instead, instructions with destination-destination dependencies are dispatched together as a group. These instructions flow down the pipelines. At the end of the pipelines the destinations are compared. If the destinations match then the results are merged together and written to the register. When instructions write to only a portion of the register, merging ensures that the correct portions of the register are written by the appropriate instructions in the group. Thus older code which performs partial-register writes can benefit from superscalar processing by dispatching the instructions together as a group and then merging the writes together at the end of the pipelines.

Abstract: A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width address components such as 16-bit address components which are effectively added together in modulo 64K. The other inputs receive full-width address components such as 32-bit components which are added in the full modulus, 4G. Reduced-width components are zero-extended to 32 bits before input to a standard 32-bit adder. A 16-bit carry generator also receives the reduced-width components and generates the carries out of the 16th bit position. When one or more carries is detected, a correction term is subtracted from the initial sum which is recirculated to the adder's input in a subsequent step. The correction term is the number of carries out of the 16th bit position multiplied by 64K.

Abstract: A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack pointer is needed for generating the stack-top address in memory. The stack-top address is generated early in the pipeline. Other stack instructions in the pipeline which have not yet incremented the stack pointer are located with a stack valid bit array. The stack valid array indicates the increment or decrement amounts for stack instructions in each pipeline stage. An overall displacement or increment value is computed as the sum of all increments and decrements for stack instructions in the pipeline which have not yet updated the stack pointer. The overall displacement which accounts for all unfinished stack instructions is added to the stack pointer from the register file to generate the stack-top address.