Abstract: A method, and apparatus are provided for controlling transition rates on adjacent interconnects in an electronic chip design. Each interconnect includes a first inverter that receives a net input and provides an initial inverted output and a second inverter coupled to the first inverter receiving the initial inverted output and providing a net output. A first compensating logic transistor stack coupled to the first inverter and a first adjacent net receives the initial inverted output and the first adjacent net input for selectively providing conductive paths. A second compensating logic transistor stack coupled to the first inverter and a second adjacent net receiving the initial inverted output and the second adjacent net input for selectively providing conductive paths.

Abstract: An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.

Abstract: An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.

Abstract: An embedded directory record and method are provided for maintaining directory information for compressed data on a direct access storage device (DASD). The embedded directory record includes a plurality of page entries, a plurality of exception region entries and a plurality of compression group statistics. Each page entry includes an allocated page length value and a number of used sectors value in the allocated page. The exception region entries include a page index and a bit map used for identifying exception sectors used. The compression group statistics include a total count of allocated sectors, a total count of the used sectors; and a total count of written pages. A starting page address for a requested page is identified beginning at a start of the page entries by summing the allocated page length values for each page up to the requested page to identify an offset value and combining the offset value with a predetermined logical block address.

Abstract: A data compression storage method and data compression hierarchical padding structure are provided for a direct access storage device (DASD) using fixed block architecture (FBA). A minimum page allocation defining a minimum number of sectors allocated for each logical compressed data page is selected. The DASD is segmented into at least one compression group. Each compression group has a fixed logical size and includes a selected number of DASD compressed data pages with an initial page allocation of a number of sectors. The initial page allocation is greater than or equal to the minimum page allocation. A minimum number of compressed data regions is allocated within each compression group. A selected number of additional compressed data regions including a plurality of sectors for padding is allocated within each compression group. The plurality of padding sectors are distributed between the compression pages. An exception region is allocated within each compression group.