Abstract: A method and system communicates payload data over a plurality of low voltage differential signaling (LVDS) channels (50). First device (100) transmits the payload data and synchronization information to the second device (150) over N LVDS channels (50), along with a word clock synchronized to the payload data. The second device generates M LVDS receive clocks from the word clock, each having a same frequency that is P times a frequency of the word clock, and each having a different phase. Each of N LVDS receivers (160) of the second device (150): correlates the synchronization data with a reference word using each of the M LVDS receive clocks to produce a correlation value for each of the M LVDS receive clocks; selects a selected LVDS receive clock producing a greatest correlation value; and receives the payload data for the corresponding LVDS channel (50) using the selected LVDS receive clock.

Abstract: A method and system communicates payload data over a plurality of low voltage differential signaling (LVDS) channels (50). First device (100) transmits the payload data and synchronization information to the second device (150) over N LVDS channels (50), along with a word clock synchronized to the payload data. The second device generates M LVDS receive clocks from the word clock, each having a same frequency that is P times a frequency of the word clock, and each having a different phase. Each of N LVDS receivers (160) of the second device (150): correlates the synchronization data with a reference word using each of the M LVDS receive clocks to produce a correlation value for each of the M LVDS receive clocks; selects a selected LVDS receive clock producing a greatest correlation value; and receives the payload data for the corresponding LVDS channel (50) using the selected LVDS receive clock.

Abstract: An efficient radio sensor and a method thereof. The radio sensor includes a first frequency tracking block (FTB) (110-i) for tracking an input narrowband signal within a predefined frequency range, wherein the first FTB is preset to a first initial frequency; a second FTB (110-j) for tracking the input narrowband signal within a predefined frequency range, wherein the second FTB is preset to a second initial frequency; a subtractor (130) for subtracting an output value of the first FTB (110-i) from an output value of the second FTB (110-j); and a comparator (140) for applying a convergence test on an output of the subtractor (130) to determine if the input narrowband signal is present.

Abstract: A digital filter includes a plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a gain that is used by each of the plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a filter cell output. An adder circuit generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.

Abstract: An apparatus and method for improving signal reception in a signal receiver is disclosed. The apparatus comprises at least two first receiver chips, a digital combiner circuit and a single third receiver chip. At least two antennae are used to receive at least two signals, the signals are passed through front end section and equalizer of the first receiver chips, wherein the quality of the signals is evaluated. The signals are combined intelligently in the digital combiner circuit based on the quality of each signal. The combined result is fed into the decoder located in the back-end section of the singe third receiver chip.

Abstract: A digital filter has a filter cell for generating processed data. The digital filter cell includes plurality of coefficient registers which are arranged to circulate a plurality of coefficient values that correspond to a plurality of coefficients such that each of the plurality of coefficients is output once during a predetermined period. One or more data registers are arranged to circulate a data value for a time which is at least as long as the predetermined period such that the data value is output each time that a different one of the plurality of coefficients is output. A circuit receives each output data value and each output coefficient and generates processed data by processing each output data value with each output coefficient.