Patents by Inventor Gene Wu

Gene Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250279962
    Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
    Type: Application
    Filed: January 3, 2025
    Publication date: September 4, 2025
    Inventors: Malek MUSLEH, Gene WU, Anupama KURPAD, Allister ALEMANIA, Roberto PENARANDA CEBRIAN, Robert SOUTHWORTH, Pedro YEBENES SEGURA, Curt E. BRUNS, Sujoy SEN
  • Patent number: 12224940
    Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Malek Musleh, Gene Wu, Anupama Kurpad, Allister Alemania, Roberto Penaranda Cebrian, Robert Southworth, Pedro Yebenes Segura, Curt E. Bruns, Sujoy Sen
  • Publication number: 20220210075
    Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 30, 2022
    Inventors: Malek MUSLEH, Gene WU, Anupama KURPAD, Allister ALEMANIA, Roberto PENARANDA CEBRIAN, Robert SOUTHWORTH, Pedro YEBENES SEGURA, Curt E. BRUNS, Sujoy SEN
  • Patent number: 10250524
    Abstract: Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Gene Wu, Michael A. Parker
  • Publication number: 20180091437
    Abstract: Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Mario Flajslik, Gene Wu, Michael A. Parker
  • Patent number: 7838424
    Abstract: An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tjandra Winata Karta, Steven Hsu, Chien-Hsiun Lee, Gene Wu, Jimmy Liang
  • Patent number: 7830004
    Abstract: A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: November 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Gene Wu
  • Patent number: 7642129
    Abstract: A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: January 5, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jimmy Liang, Gene Wu, Steven Hsu
  • Publication number: 20090011543
    Abstract: An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
    Type: Application
    Filed: July 3, 2007
    Publication date: January 8, 2009
    Inventors: Tjandra Winata Karta, Steven Hsu, Chien-Hsiun Lee, Gene Wu, Jimmy Liang
  • Publication number: 20080160671
    Abstract: A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Inventors: Jimmy Liang, Gene Wu, Steven Hsu
  • Publication number: 20080131996
    Abstract: A reverse build-up method for forming a package substrate includes forming bumps; forming an interconnect structure connected to the bumps; and forming ball grid array (BGA) balls on the interconnect structure. The BGA balls are electrically connected to the bumps through the interconnect structure. The step of forming the bumps are performed before the steps of forming the interconnect structure and forming the BGA balls.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventor: Gene Wu
  • Publication number: 20080099912
    Abstract: A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Inventor: Gene Wu