Abstract: The invention relates to the technical field of computer-aided design of integrated circuits, and provides a two-step X-architecture Steiner minimum tree construction method for very large scale integration (VLSI). Based on the advantages of an X-architecture model and a particle swarm optimization technique, the method is implemented through two steps: (1) the stage of social learning discrete particle swarm search, which comprises: using an edge-vertex encoding strategy capable of maintaining optimal topological information of particles, designing a fitness function taking wirelength into consideration; and using a chaotic decreasing mutation strategy and a new social learning strategy to design a new discrete particle swarm update formula; and (2) a stage of wirelength optimization, which comprises: designing a local topological optimization strategy to minimize the wirelength of an X-architecture Steiner tree.

Abstract: A DRL-based control logic design method for continuous microfluidic biochips is provided. Firstly, an integer linear programming model is for effectively solving multi-channel switching calculation to minimize the number of time slices required by the control logic. Secondly, a control logic synthesis method based on deep reinforcement learning, which uses a double deep Q network and two Boolean logic simplification techniques to find a more effective pattern allocation scheme for the control logic.

Abstract: The invention relates to the technical field of computer-aided design of integrated circuits, and provides a two-step X-architecture Steiner minimum tree construction method for very large scale integration (VLSI). Based on the advantages of an X-architecture model and a particle swarm optimization technique, the method is implemented through two steps: (1) the stage of social learning discrete particle swarm search, which comprises: using an edge-vertex encoding strategy capable of maintaining optimal topological information of particles, designing a fitness function taking wirelength into consideration; and using a chaotic decreasing mutation strategy and a new social learning strategy to design a new discrete particle swarm update formula; and (2) a stage of wirelength optimization, which comprises: designing a local topological optimization strategy to minimize the wirelength of an X-architecture Steiner tree.

Abstract: A multi-stage FPGA routing method for optimizing time division multiplexing comprises the following steps: S1: collecting an FPGA set, an FPGA connection pair set, a net set and a net group set; S2: acquiring a routing topology of each net according to the FPGA set, the FPGA connection pair set, the net set and the net group set under the condition where TRs are not assigned; S3: assigning a corresponding TR to each edge of each net according to different delay of each net group; and S4: performing TR reduction and edge validation cyclically, iteratively optimizing net groups with TR being greater than a preset value until iteration end conditions are met, so as to obtain an optimal routing result. The multi-stage FPGA routing method may optimize the delay of inter-chip signals of a multi-FPGA prototype system and guarantee the routability of the multi-FPGA prototype system.