Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.

Abstract: Certain aspects of the present disclosure generally relate to a high electron mobility transistor and techniques for fabricating the same. Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate; a channel region having a fin disposed above the substrate; a first barrier layer disposed adjacent to a first side and a second side of the first fin, wherein the first side and the second side of the first fin are opposite sides, the first barrier layer forming a heterojunction with the fin; a first dielectric layer disposed adjacent to a first side and a second side of the first barrier layer, wherein the first side and the second side of the first barrier layer are opposite sides; and a first gate region disposed adjacent to the first dielectric layer.

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis andY-axis dimensions of the horizontal footprint are reduced.

Abstract: A photo detector comprises a first photo diode configured to capture visible light, a second photo diode configured to capture one of infrared light or ultraviolet light, and an isolation region between the first photo diode and the second photo diode. The photo detector is capable of capturing infrared light and ultraviolet light in addition to visible light.

Abstract: A horizontal gate-all-around (GAA) field effect transistor (FET) is described. The horizontal GAA FET includes a substrate as well as a shallow trench isolation (STI) region on the substrate. The horizontal GAA FET includes a first nano-sheet structure on the substrate and extending through the STI region. The first nano-sheet structure includes a first drain/source region stacked on a first source/drain region. The first nano-sheet structure also includes a first channel region between the first drain/source region and the first source/drain region. The horizontal GAA FET also includes a first gate on the STI region and horizontally surrounding the first channel region on four sides.

Abstract: A photo detector comprises a first photo diode configured to capture visible light, a second photo diode configured to capture one of infrared light or ultraviolet light, and an isolation region between the first photo diode and the second photo diode. The photo detector is capable of capturing infrared light and ultraviolet light in addition to visible light.

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

Abstract: A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts.

Abstract: In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.

Abstract: A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.

Abstract: Three-dimensional (3D) carbon nanotube gate field-effect transistors (FETs), that use carbon nanotubes to form a gate, and related fabrication methods are disclosed. A carbon nanotube gate can provide for greater channel control and enlarge the effective channel width of the 3D FET, thus increasing drive strength. Carbon nanotubes have lower surface scatter and have been found to be diffusive such that resistance dominates carrier transport, thus causing higher carrier mobility. A 3D FET can be provided that includes a gate formed from carbon nanotube(s) disposed adjacent to a semiconductor channel formed from a carbon nanotube(s). A dual-gate FET can be provided employing a carbon nanotube gate(s) comprising a front and back carbon nanotube with a semiconductor channel formed therebetween.

Abstract: Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies.

Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

Abstract: A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.