Patents by Inventor Gengyu Yang
Gengyu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848555Abstract: The disclosure relates to a method and system for evaluating the stability of HVDC receiving end system and storage medium, which relates to the technical field of high voltage direct current transmission. The method includes: collecting voltage at a generator port, current at the generator port and rotational speed of the generator after eliminating fault; determining a corresponding relationship between the generator dynamic energy and the time according to the voltage at the generator port, the current at the generator port and the rotational speed of the generator; determining the attenuation intensity of the generator dynamic energy according to the corresponding relationship between the generator dynamic energy and the time; determining stability of the HVDC receiving end system according to the attenuation intensity of the generator dynamic energy.Type: GrantFiled: July 9, 2021Date of Patent: December 19, 2023Assignee: NORTH CHINA ELECTRIC POWER UNIVERSITYInventors: Jing Ma, Gengyu Yang, Ruifeng Wang, Yuchong Wu
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Publication number: 20220021213Abstract: The disclosure relates to a method and system for evaluating the stability of HVDC receiving end system and storage medium, which relates to the technical field of high voltage direct current transmission. The method includes: collecting voltage at a generator port, current at the generator port and rotational speed of the generator after eliminating fault; determining a corresponding relationship between the generator dynamic energy and the time according to the voltage at the generator port, the current at the generator port and the rotational speed of the generator; determining the attenuation intensity of the generator dynamic energy according to the corresponding relationship between the generator dynamic energy and the time; determining stability of the HVDC receiving end system according to the attenuation intensity of the generator dynamic energy.Type: ApplicationFiled: July 9, 2021Publication date: January 20, 2022Applicant: NORTH CHINA ELECTRIC POWER UNIVERSITYInventors: Jing MA, Gengyu YANG, Ruifeng WANG, Yuchong WU
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Publication number: 20140145139Abstract: The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.Type: ApplicationFiled: February 22, 2012Publication date: May 29, 2014Inventors: Ru Huang, Yu Tang, Yimao Cai, Lijie Zhang, Gengyu Yang, Shenghu Tan, Yue Pan, Poren Tang
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Patent number: 8633465Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.Type: GrantFiled: February 8, 2012Date of Patent: January 21, 2014Assignee: Peking UniversityInventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
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Patent number: 8564031Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).Type: GrantFiled: April 1, 2011Date of Patent: October 22, 2013Assignee: Peking UniversityInventors: Ru Huang, Jibin Zou, Runsheng Wang, Gengyu Yang, Yujie Ai, Jiewen Fan
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Patent number: 8526242Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process.Type: GrantFiled: March 7, 2011Date of Patent: September 3, 2013Assignee: Peking UniversityInventors: Ru Huang, Yimao Cai, Shiqiang Qin, Qianqian Huang, Poren Tang, Yu Tang, Gengyu Yang
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Publication number: 20130217199Abstract: The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.Type: ApplicationFiled: April 16, 2012Publication date: August 22, 2013Applicant: PEKING UNIVERSITYInventors: Ru Huang, Shenghu Tan, Lijie Zhang, Yue Pan, Yinglong Huang, Gengyu Yang, Yu Tang, Jun Mao, Yimao Cai
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Publication number: 20130069031Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.Type: ApplicationFiled: February 8, 2012Publication date: March 21, 2013Applicant: PEKING UNIVERSITY NO. 5 YIHEYUAN ROAD HAIDIAN DISTRICTInventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
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Publication number: 20120199808Abstract: The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices.Type: ApplicationFiled: April 1, 2011Publication date: August 9, 2012Inventors: Ru Huang, Jibin Zou, Runsheng Wang, Gengyu Yang, Yujie Al, Jiewen Fan
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Publication number: 20120113726Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process.Type: ApplicationFiled: March 7, 2011Publication date: May 10, 2012Applicant: PEKING UNIVERSITYInventors: Ru Huang, Yimao Cai, Shiqiang Qin, Qianqian Huang, Poren Tang, Yu Tang, Gengyu Yang