Abstract: A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Abstract: To provide a semiconductor integrated circuit in which a clock signal supplied to each flip-flop will not be adversely affected when a functional change is made using a spare flip-flop. The semiconductor integrated circuit includes a plurality of main flip-flops which contribute to a predetermined function, a plurality of spare flip-flops, and a clock tree synthesis circuit that generates a clock signal which is adjusted for synchronizing the plurality of main flip-flops and the plurality of spare flip-flops and supplies the adjusted clock signal to the plurality of main flip-flops and the plurality of spare flip-flops.

Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a mater latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Abstract: A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Abstract: To provide a semiconductor integrated circuit in which a clock signal supplied to each flip-flop will not be adversely affected when a functional change is made using a spare flip-flop. The semiconductor integrated circuit includes a plurality of main flip-flops which contribute to a predetermined function, a plurality of spare flip-flops, and a clock tree synthesis circuit that generates a clock signal which is adjusted for synchronizing the plurality of main flip-flops and the plurality of spare flip-flops and supplies the adjusted clock signal to the plurality of main flip-flops and the plurality of spare flip-flops.

Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a mater latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Abstract: The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.

Abstract: The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.

Abstract: To provide a data backup memory that can function, when used to design an LSI, for a circuit operating at a frequency double that of a clock provided. The data backup memory includes a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit. It can maintain and improve the characteristics of conventional data backup memories that the setup time therefor is ideally zero and that the worst value of a delay time can be designed to be small, while enabling data processing both at a rising and a falling edges of a clock signal.

Abstract: To provide a data backup memory that can function, when used to design an LSI, for a circuit operating at a frequency double that of a clock provided. The data backup memory includes a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit. It can maintain and improve the characteristics of conventional data backup memories that the setup time therefor is ideally zero and that the worst value of a delay time can be designed to be small, while enabling data processing both at a rising and a falling edges of a clock signal.

Abstract: To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit.

Abstract: In the case of addition/subtraction of floating-point numbers, two mantissas having their digits aligned in a swapper and in a right shifter are supplied to an adder/subtracter via first and second mantissa selectors and two 1-bit right shifters so that they are subjected to addition/subtraction in the adder/subtracter, the result of which is rounded. In the case of multiplication/division of floating-point numbers, an intermediate sum and a carry, each outputted from a multiplier, are supplied to the above adder/subtracter via the above first and second mantissa selectors and the above two 1-bit right shifters, so that they are added in the adder/subtracter, the result of which is rounded. The result of rounding from the adder/subtracter is outputted as a normalized mantissa through a priority encoder and a left shifter. An exponent is processed by first to third exponent arithmetic units and an exponent selector.

Abstract: The present invention discloses a multiplication device. A multiplicand X of eight bits and a multiplier Y of eight bits are input and a product P of sixteen bits is found from these multiplication factors. MULTIPLICAND X is divided into two parts, an upper-order part X.sub.U of four bits and a low-order part X.sub.L of four bits. MULTIPLIER Y is likewise divided into two parts, an upper-order part Y.sub.U of four bits and a low-order part Y.sub.L of four bits. Thereafter, four 8-bit partial products, i.e., X.sub.L .times.Y.sub.L, X.sub.L .times.Y.sub.U, X.sub.U .times.Y.sub.L, and X.sub.U .times.Y.sub.U are computed one after another. These partial products are subjected to a digit place alignment addition operation, by an adder, to compute PRODUCT P. Computation of each of the partial products is implemented by performing addition of an approximate partial product AP retrieved by a 6-bit address from a 64-byte ROM, and a correction value H and a carry C generated by a correction value generator.

Abstract: A bit-discard amount anticipator anticipates a bit-discard amount within a one-bit error. A borrow propagator propagates a borrow from a least significant bit side. A selector modifies an output of the bit-discard amount anticipator to an accurate bit shift amount required at a normalization and outputs it, using information of the borrow propagator. The bit shift amount for the normalization in case where a bit discard is caused at a mantissa subtraction of a floating point calculation is accurately obtained, thus reducing a process at the normalization.