Abstract: A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Abstract: A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.

Abstract: A film forming method includes: a loading process of loading a substrate into a processing container; a first process of forming an interface layer having an amorphous structure or a microcrystalline structure on the substrate by plasma of a first mixed gas including a carbon-containing gas; and a second process of forming a graphene film on the interface layer by plasma of a second mixed gas including the carbon-containing gas.

Abstract: A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.

Abstract: A semiconductor device includes an electric-charge storing film, an electrode, a first block film, and a second block film. The first block film is arranged between the electric-charge storing film and the electrode. The second block film is arranged between the first block film and the electric-charge storing film. The first block film is an oxide film containing tantalum, and an electric permittivity of the first block film is larger than an electric permittivity of the second block film.

Abstract: A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Abstract: A plurality of embodiments for ReRAM devices and method of making are described. According to one embodiment, the ReRAM device includes a first electrode film formed on a substrate, a metal oxide film with oxygen vacancies formed on a first electrode film, a conformal TiAlC film, oxidized by diffused oxygen atoms from the metal oxide film, formed on the metal oxide film, and a second electrode film formed on the TiAlC film. According to another embodiment, the ReRAM device includes a pair of vertical metal oxide films, a pair of vertical conformal TiAlC films formed on the pair of vertical metal oxide films, the pair of vertical conformal TiAlC films oxidized by diffused oxygen atoms from the pair of vertical metal oxide films, and an electrode film formed between the pair of vertical conformal TiAlC films.

Abstract: A plurality of embodiments for ReRAM devices and method of making are described. According to one embodiment, the ReRAM device includes a first electrode film formed on a substrate, a metal oxide film with oxygen vacancies formed on a first electrode film, a conformal TiAlC film, oxidized by diffused oxygen atoms from the metal oxide film, formed on the metal oxide film, and a second electrode film formed on the TiAlC film. According to another embodiment, the ReRAM device includes a pair of vertical metal oxide films, a pair of vertical conformal TiAlC films formed on the pair of vertical metal oxide films, the pair of vertical conformal TiAlC films oxidized by diffused oxygen atoms from the pair of vertical metal oxide films, and an electrode film formed between the pair of vertical conformal TiAlC films.

Abstract: A nonvolatile storage device includes: first wirings arranged in first and second directions that intersect each other, and extending in a third direction perpendicular to the first and second directions; second wirings extending in the first direction, and each of the second wiring installed at a predetermined interval from each other in the third direction; first layers disposed between the first wirings and the second wirings, and extending in the third direction along the plurality of first wirings; and memory cells installed between the first layers and the second wirings and at respective positions where the first layers and the second wirings intersect each other. Each memory cell includes a second layer disposed towards a side closer to the second wirings and a conductive intermediate layer disposed towards a side closer to the first layers.

Abstract: Embodiments of the invention describe parasitic capacitance reduction structure for nanowire transistors and method of manufacturing. According to one embodiment the method includes providing a substrate, forming a first nanowire on the substrate, forming a second nanowire on the first nanowire, forming a first dielectric layer between the substrate and the first nanowire, and forming a second dielectric layer between first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer. According to one embodiment, a nanowire transistor includes a first nanowire on a substrate, a second nanowire on the second nanowire, a first dielectric layer between the substrate and the first nanowire, and a second dielectric layer between the first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer.

Abstract: A method for manufacturing an insulating film laminated structure includes a step of forming a first high-k film on a semiconductor substrate, a step of processing the semiconductor substrate in a processing chamber of a plasma processing apparatus by using a plasma to form an oxide film on an interface between the semiconductor substrate and the first high-k film, and a step of forming a second high-k film on the first high-k film. A plasma oxidation process is performed by using a plasma of an oxygen-containing gas at a processing temperature of the semiconductor substrate in a range from 20° C. to 145° C. while setting a power density of a total power of microwaves to be within a range from 0.035 kW/m2 to 3.5 kW/m2 with respect to a total area of a conductive member facing an inner space of the processing chamber and microwave transmitting windows.

Abstract: Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer. The method further includes e) repeating a)-d) at least once, f) following e), repeating a)-c) once, g) etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure, and h) removing the patterned first semiconductor layers from the fin structure.

Abstract: A method of forming a semiconductor device is disclosed in various embodiments. The method includes providing a substrate containing first and second device regions, and a high-k film on the substrate, depositing a metal nitride gate electrode film on the high-k film, forming a metal-containing gate electrode film on the metal nitride gate electrode film in the second device region but not in the first device region, and depositing a Si-based cap layer on the metal-containing gate electrode film in the second device region and on the metal nitride gate electrode film in the first device region.

Abstract: A method for manufacturing an insulating film laminated structure includes a step of forming a first high-k film on a semiconductor substrate, a step of processing the semiconductor substrate in a processing chamber of a plasma processing apparatus by using a plasma to form an oxide film on an interface between the semiconductor substrate and the first high-k film, and a step of forming a second high-k film on the first high-k film. A plasma oxidation process is performed by using a plasma of an oxygen-containing gas at a processing temperature of the semiconductor substrate in a range from 20° C. to 145° C. while setting a power density of a total power of microwaves to be within a range from 0.035 kW/m2 to 3.5 kW/m2 with respect to a total area of a conductive member facing an inner space of the processing chamber and microwave transmitting windows.

Abstract: Disclosed is a method of manufacturing a semiconductor element by implanting a dopant to a substrate to be processed. High frequency plasma is generated within a processing container by using microwaves. By using the generated high frequency plasma, a plasma doping treatment is performed on a germanium-containing to-be-processed substrate which is held on a holding table within the processing container.

Abstract: Embodiments of the invention describe parasitic capacitance reduction structure for nanowire transistors and method of manufacturing. According to one embodiment the method includes providing a substrate, forming a first nanowire on the substrate, forming a second nanowire on the first nanowire, forming a first dielectric layer between the substrate and the first nanowire, and forming a second dielectric layer between first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer. According to one embodiment, a nanowire transistor includes a first nanowire on a substrate, a second nanowire on the second nanowire, a first dielectric layer between the substrate and the first nanowire, and a second dielectric layer between the first dielectric layer and the second nanowire, where the second dielectric layer has a higher dielectric constant than the first dielectric layer.

Abstract: Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer. The method further includes e) repeating a)-d) at least once, f) following e), repeating a)-c) once, g) etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure, and h) removing the patterned first semiconductor layers from the fin structure.

Abstract: A method of forming a semiconductor device is disclosed in various embodiments. The method includes providing a substrate containing first and second device regions, and a high-k film on the substrate, depositing a metal nitride gate electrode film on the high-k film, forming a metal-containing gate electrode film on the metal nitride gate electrode film in the second device region but not in the first device region, and depositing a Si-based cap layer on the metal-containing gate electrode film in the second device region and on the metal nitride gate electrode film in the first device region.

Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.

Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.