Patents by Inventor Genki Fujita
Genki Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038731Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: October 13, 2023Publication date: February 1, 2024Applicant: KIOXIA CORPORATIONInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 11817428Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: February 1, 2022Date of Patent: November 14, 2023Assignee: KIOXIA CORPORATIONInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20220157784Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Applicant: KIOXIA CORPORATIONInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 11270980Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: June 30, 2020Date of Patent: March 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20200350291Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: June 30, 2020Publication date: November 5, 2020Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 10741527Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: April 22, 2019Date of Patent: August 11, 2020Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20190312012Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: April 22, 2019Publication date: October 10, 2019Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 10297578Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: September 15, 2017Date of Patent: May 21, 2019Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20180261575Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: September 15, 2017Publication date: September 13, 2018Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita