Patents by Inventor Genki KAWAGUCHI
Genki KAWAGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11895844Abstract: A semiconductor memory device according to an embodiment includes a substrate including block areas, members, conductive layers, and pillars. Each of the members is respectively disposed at a boundary portion between the block areas. At least one member of the members includes first portions and a second portion. The first portions are arranged in a first direction. The second portion is disposed between any two adjacent ones of the first portions. Either one of one of the first portions and the second portion of the member is referred to as a third portion. The other one of the one of the first portions and the second portion of the member is referred to as a fourth portion. The third portion has a width in a second direction greater than a width of the fourth portion in the second direction.Type: GrantFiled: March 12, 2021Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventor: Genki Kawaguchi
-
Patent number: 11672112Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.Type: GrantFiled: August 6, 2020Date of Patent: June 6, 2023Assignee: Kioxia CorporationInventors: Genki Kawaguchi, Yasuhito Yoshimizu, Yusuke Shima
-
Patent number: 11631693Abstract: According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.Type: GrantFiled: August 14, 2020Date of Patent: April 18, 2023Assignee: Kioxia CorporationInventors: Takahito Nishimura, Genki Kawaguchi, Yusuke Okumura
-
Publication number: 20230079009Abstract: A memory device includes: a substrate having a memory region and an external region; a first conductor, in the memory region, being arranged apart from the substrate in a first direction; second and third conductors, in the external region, being arranged apart from the first conductor in a second direction; a first member between the first and second conductors; a second member between the second and third conductors; and an insulating member between the first and second members. The first and second members each includes a lower portion extending in the first direction and reaching below the second conductor and an upper portion having a side surface outside an extension of a side surface of the lower portion. The insulating member includes lower and upper ends located below and above each of the upper portions, respectively.Type: ApplicationFiled: February 11, 2022Publication date: March 16, 2023Applicant: Kioxia CorporationInventors: Nozomi KARYU, Genki KAWAGUCHI
-
Patent number: 11587850Abstract: According to one embodiment, a semiconductor storage device includes: first and second plate-shaped portions which extend in a stacking direction of each layer of a first stacked body and a first direction intersecting the stacking direction and are arranged between the first stacked body and a second stacked body on both sides of the second stacked body in a second direction intersecting the stacking direction and the first direction; and an isolation layer that penetrates at least the uppermost conductive layer among a plurality of conductive layers and isolates the uppermost conductive layer in the second direction. The isolation layer extends in a portion of the first stacked body in the first direction toward the second stacked body, and is connected to a side surface of the first plate-shaped portion from a first region on an inner side of the first and second plate-shaped portions.Type: GrantFiled: March 12, 2021Date of Patent: February 21, 2023Assignee: Kioxia CorporationInventors: Nozomi Karyu, Genki Kawaguchi
-
Patent number: 11569253Abstract: A semiconductor memory device includes multiple first electrode layers stacked in a first direction, multiple second electrode layers stacked in the first direction, a first columnar body extending through the multiple first electrode layers in the first direction, a second columnar body extending through the multiple second electrode layers in the first direction, a connection part connecting the first columnar body and the second columnar body, and a spacer film having an island configuration surrounding the connection part. The multiple first electrode layers and the multiple second electrode layers are arranged in the first direction, and the connection part and the spacer film are provided between the multiple first electrode layers and the multiple second electrode layers.Type: GrantFiled: September 1, 2020Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Takeshi Nagatomo, Tatsuo Izumi, Ryota Suzuki, Takuya Nishikawa, Yasuhito Nakajima, Daiki Takayama, Hiroaki Naito, Genki Kawaguchi
-
Publication number: 20220415787Abstract: According to one embodiment, a semiconductor memory device includes a substrate expanding in a first direction and a second direction, a plurality of conductive layers arranged in a third direction with a distance therebetween, the conductive layers including a first conductive layer, and each including a first portion and a second portion being arranged with the first portion in the second direction and including a terrace portion provided so as not to overlap an upper conductive layer in the third direction, a first insulating portion provided between the first portions and the second portions, and a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween.Type: ApplicationFiled: February 3, 2022Publication date: December 29, 2022Applicant: Kioxia CorporationInventor: Genki KAWAGUCHI
-
Publication number: 20220084910Abstract: According to one embodiment, a semiconductor storage device includes: first and second plate-shaped portions which extend in a stacking direction of each layer of a first stacked body and a first direction intersecting the stacking direction and are arranged between the first stacked body and a second stacked body on both sides of the second stacked body in a second direction intersecting the stacking direction and the first direction; and an isolation layer that penetrates at least the uppermost conductive layer among a plurality of conductive layers and isolates the uppermost conductive layer in the second direction. The isolation layer extends in a portion of the first stacked body in the first direction toward the second stacked body, and is connected to a side surface of the first plate-shaped portion from a first region on an inner side of the first and second plate-shaped portions.Type: ApplicationFiled: March 12, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Nozomi KARYU, Genki KAWAGUCHI
-
Publication number: 20220052068Abstract: A semiconductor memory device according to an embodiment includes a substrate including block areas, members, conductive layers, and pillars. Each of the members is respectively disposed at a boundary portion between the block areas. At least one member of the members includes first portions and a second portion. The first portions are arranged in a first direction. The second portion is disposed between any two adjacent ones of the first portions. Either one of one of the first portions and the second portion of the member is referred to as a third portion. The other one of the one of the first portions and the second portion of the member is referred to as a fourth portion. The third portion has a width in a second direction greater than a width of the fourth portion in the second direction.Type: ApplicationFiled: March 12, 2021Publication date: February 17, 2022Applicant: Kioxia CorporationInventor: Genki KAWAGUCHI
-
Publication number: 20220020681Abstract: A semiconductor memory device according to an embodiment includes a substrate. The substrate includes first and second areas, and block areas. The second area includes subareas. Each of the subareas includes a contact area and an insulating area arranged in the first direction. The contact area includes terraced portions and first contacts corresponding to two block areas. The insulating area includes second contacts corresponding to the two block areas. Contact areas of odd-numbered subareas and insulating areas of even-numbered subareas are disposed in an alternating manner in the second direction. Insulating areas of the odd-numbered subareas and contact areas of the even-numbered subareas are disposed in an alternating manner in the second direction.Type: ApplicationFiled: January 11, 2021Publication date: January 20, 2022Applicant: Kioxia CorporationInventors: Kazuhiro NOJIMA, Genki KAWAGUCHI
-
Publication number: 20210288064Abstract: According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.Type: ApplicationFiled: August 14, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Takahito NISHIMURA, Genki KAWAGUCHI, Yusuke OKUMURA
-
Publication number: 20210043640Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.Type: ApplicationFiled: August 6, 2020Publication date: February 11, 2021Applicant: Kioxia CorporationInventors: Genki KAWAGUCHI, Yasuhito YOSHIMIZU, Yusuke SHIMA
-
Publication number: 20200395371Abstract: A semiconductor memory device includes multiple first electrode layers stacked in a first direction, multiple second electrode layers stacked in the first direction, a first columnar body extending through the multiple first electrode layers in the first direction, a second columnar body extending through the multiple second electrode layers in the first direction, a connection part connecting the first columnar body and the second columnar body, and a spacer film having an island configuration surrounding the connection part. The multiple first electrode layers and the multiple second electrode layers are arranged in the first direction, and the connection part and the spacer film are provided between the multiple first electrode layers and the multiple second electrode layers.Type: ApplicationFiled: September 1, 2020Publication date: December 17, 2020Inventors: Takeshi NAGATOMO, Tatsuo Izumi, Ryota Suzuki, Takuya Nishikawa, Yasuhito Nakajima, Daiki Takayama, Hiroaki Naito, Genki Kawaguchi
-
Patent number: 10797077Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: December 3, 2019Date of Patent: October 6, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
-
Publication number: 20200111809Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: December 3, 2019Publication date: April 9, 2020Applicant: Toshiba Memory CorporationInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
-
Patent number: 10541251Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: July 23, 2018Date of Patent: January 21, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
-
Publication number: 20180350834Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: July 23, 2018Publication date: December 6, 2018Applicant: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
-
Patent number: 10074665Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: September 6, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Genki Kawaguchi, Masanori Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
-
Publication number: 20170077108Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: September 6, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
-
Publication number: 20120126306Abstract: According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.Type: ApplicationFiled: September 21, 2011Publication date: May 24, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Genki KAWAGUCHI, Fumitaka Arai, Satoshi Nagashima, Naoki Kai, Wataru Sakamoto, Hiroyuki Nitta