Patents by Inventor Genki Yano

Genki Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122296
    Abstract: Footwear includes a sole portion that supports a foot sole of a foot of a wearer, the sole portion including a ground contact surface and a shock absorbing portion formed of an elastic body. The shock absorbing portion includes a three-dimensional mesh structure portion in which a plurality of unit structures are repeatedly arranged so as to be adjacent to each other and an irregularly shaped portion that has a different shape from each of the unit structures and is at least partially embedded in the three-dimensional mesh structure portion. The irregularly shaped portion includes a protruding plate portion in which a central portion protrudes relative to a peripheral edge portion in a direction orthogonal to the ground contact surface.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Inventors: Yuka MATSUHISA, Seiji YANO, Kenji HIRATA, Genki HATANO
  • Publication number: 20240122295
    Abstract: Footwear includes a shell including an outsole portion; and a sole body including a footbed portion. The footbed portion includes a shock absorbing portion formed of a three-dimensional mesh structure body so as to extend to a peripheral surface of the footbed portion. An engaged portion is disposed in an inner side surface of the outsole portion, and an engaging portion is disposed in a portion of the shock absorbing portion that corresponds to the peripheral surface. One of the engaged portion and the engaging portion is a protruding portion while the other one of the engaged portion and the engaging portion is a cutout portion provided as a recessed portion or a hole portion. An occupied volume ratio of a region including at least a portion defining the engaging portion in the shock absorbing portion is locally increased.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Inventors: Yuka MATSUHISA, Seiji YANO, Kenji HIRATA, Genki HATANO
  • Publication number: 20240122297
    Abstract: Footwear includes a footbed portion including a support region. The support region includes an upper surface-side projection portion forming region having a plurality of upper surface-side projection portions. A maximum outer dimension in a cross-section orthogonal to a projecting direction of each of the plurality of upper surface-side projection portions is not greater than 3.0 mm. A projection length of each of the plurality of upper surface-side projection portions is not less than 4.0 mm and not greater than 13.0 mm, and an arrangement density of the plurality of upper surface-side projection portions in the upper surface-side projection portion forming region is not less than 10% and not greater than 100% in terms of an area ratio. An elastic modulus of a material forming the plurality of upper surface-side projection portions is not less than 0.1 MPa and not greater than 100 MPa.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Inventors: Yuka MATSUHISA, Seiji YANO, Kenji HIRATA, Genki HATANO
  • Publication number: 20230260839
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
  • Patent number: 11664276
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 30, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Christopher Daniel Manack, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Ming Zhu, Joseph O. Liu
  • Publication number: 20230040267
    Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.
    Type: Application
    Filed: October 5, 2022
    Publication date: February 9, 2023
    Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Patent number: 11498831
    Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Peter Wachtler, Makoto Yoshino, Ayumu Kuroda, Brian E. Goodlin, Karen Kirmse, Benjamin Cook, Genki Yano, Stuart Jacobsen
  • Patent number: 11482442
    Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 25, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Patent number: 11469141
    Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Patent number: 11367699
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Yi Yan, Hau Nguyen
  • Patent number: 11171031
    Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano
  • Publication number: 20210183683
    Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.
    Type: Application
    Filed: February 24, 2021
    Publication date: June 17, 2021
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Publication number: 20210035932
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Application
    Filed: September 1, 2020
    Publication date: February 4, 2021
    Inventors: Hiroyuki SADA, Shoichi IRIGUCHI, Genki YANO, Luu Thanh NGUYEN, Ashok PRABHU, Anindya PODDAR, Yi YAN, Hau NGUYEN
  • Publication number: 20200354214
    Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventors: Kurt Peter Wachtler, Makoto Yoshino, Ayumu Kuroda, Brian E. Goodlin, Karen Kirmse, Benjamin Cook, Genki Yano, Stuart Jacobsen
  • Patent number: 10763230
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Yi Yan, Hau Nguyen
  • Patent number: 10723616
    Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Peter Wachtler, Makoto Yoshino, Ayumu Kuroda, Brian E. Goodlin, Karen Kirmse, Benjamin Cook, Genki Yano, Stuart Jacobsen
  • Publication number: 20200203295
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Hiroyuki SADA, Shoichi IRIGUCHI, Genki YANO, Luu Thanh NGUYEN, Ashok PRABHU, Anindya PODDAR, Yi YAN, Hau NGUYEN
  • Publication number: 20200176314
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
  • Patent number: 10658240
    Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shoichi Iriguchi, Hiroyuki Sada, Genki Yano
  • Publication number: 20200075386
    Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, SADA HIROYUKI, SHOICHI IRIGUCHI, GENKI YANO