Patents by Inventor Genshu Fuse

Genshu Fuse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9023720
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 5, 2015
    Assignee: Sen Corporation
    Inventors: Genshu Fuse, Michiro Sugitani
  • Patent number: 8163635
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Sen Corporation
    Inventors: Michiro Sugitani, Genshu Fuse
  • Publication number: 20120052664
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Application
    Filed: August 25, 2011
    Publication date: March 1, 2012
    Applicant: SEN CORPORATION
    Inventors: Genshu FUSE, Michiro Sugitani
  • Publication number: 20110136329
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 9, 2011
    Applicant: SEN Corporation
    Inventors: Michiro SUGITANI, Genshu Fuse
  • Patent number: 5476006
    Abstract: Crystal evaluation apparatus is disclosed which includes a cell region having an anode and a cathode, a reservoir tank for supplying of an aqueous solution for forming an anodic oxide film in the cell region, a reservoir tank for supplying of an aqueous solution for removing the anodic oxide film and a scanning microprobe microscope having a scanning microprobe, installed inside the cell region. A crystal evaluation method is also disclosed which contains anodic oxidation on a semiconductor substrate, removal of an anodic oxide film developed. The semiconductor substrate is observed with a scanning probe microscope having a scanning microprobe. The oxide film is formed on the semiconductor substrate by the anodic oxidation method and then removed by a mixture of hydrofluoric acid and ammonium fluoride. The anodic oxidation method exerts no or little physical impact on the substrate.
    Type: Grant
    Filed: July 7, 1993
    Date of Patent: December 19, 1995
    Assignee: Matsushita Electronics Corporation
    Inventors: Shingi Fujii, Genshu Fuse, Morio Inoue
  • Patent number: 5466612
    Abstract: A dielectric film is formed on a P type silicon substrate. Then a specified resist pattern is formed on the dielectric film. Using this resist pattern as the mask, a phosphorus ion beam is implanted. Then, removing the resist pattern, heat treatment is given. By this heat treatment, a photo diode is formed in a depth of about 1 .mu.m. A specified resist pattern is formed again on the dielectric film. Using this resist pattern as the mask, boron ions are implanted. Thus, a channel stopper region is formed. Afterwards, removing the resist pattern, the dielectric film is removed. Again, a dielectric film is formed on the silicon substrate. Later, a stacked oxide film is formed in the other regions than the region for forming the photo diode on the dielectric film. Using the stacked oxide film as the mask, a boron ion beam is implanted.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: November 14, 1995
    Assignee: Matsushita Electronics Corp.
    Inventors: Genshu Fuse, Katuya Ishikawa
  • Patent number: 5270226
    Abstract: By symmetrically forming source and drain regions to the gate electrodes, electrically symmetrical transistor characteristics are obtained. After forming the first source and drain regions by large-tilt-angle ion implantation, without a sidewall in the gate electrode or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the mask for ion implantation, the diffusion of the second source and drain regions in the lateral direction is restricted to the maximum extent by heat treatment for a short time, and then the end of the gate electrode and the end of the second source and drain regions are matched, or their overlap region is formed. As a result, the manufacturing method of the MOS transistor results in both high performance and high reliability.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: December 14, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Hori, Toshiki Yabu, Kazumi Kurimoto, Genshu Fuse
  • Patent number: 5270227
    Abstract: An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as "voids 21" which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: December 14, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuichi Kameyama, Genshu Fuse
  • Patent number: 5223445
    Abstract: An ion implanting method which suppresses defects by changing the shape of the amorphous layer formed by ion injection from that of a conventional device.After forming a mask pattern on a semiconductor wafer, amorphous layers are then formed with sufficient penetration under the mask material by implanting ions at an implant angle greater than or equal to 20 degrees with a dose amount enough for forming amorphous layers. In this large angle ion implanting method, the edge of each amorphous layer becomes dull and, thereby, no voids are formed in a successive heat treatment.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: June 29, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Genshu Fuse
  • Patent number: 5057444
    Abstract: A method of fabricating a semiconductor device comprising a step of forming a trench selectively on a semiconductor substrate, a step of positioning said semiconductor substrate to a first position inclined to a plane vertical to ion beams, a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the first position, a step of positioning said semiconductor substrate to a second position which is different from the first position by rotating it, and a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the second position.
    Type: Grant
    Filed: January 19, 1990
    Date of Patent: October 15, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Takashi Ohzone
  • Patent number: 5049518
    Abstract: A semiconductor memory, particularly, a dynamic RAM, is provided having a two-cell one-contact memory cell connection structure. A connection portion between memory cells in a silicon substrate of a dynamic RAM, wherein each memory cell has one silicon island enclosed by a trench and provided with two transistor cells within said island, is formed by connecting a polysilicon electrode, enclosing the periphery of the silicon island at the inside of the trench and separated at two portions of the periphery of the silicon island, to the source or drain of one of the two transistor cells of the memory cell. The connection of the polysilicon electrode to the source or drain of the transistor cell of each of two adjacent memory cells can be easily achieved through self aligning by using a fine-trench polysilicon burying method or a selective epitaxial method.
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: September 17, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Genshu Fuse
  • Patent number: 5026658
    Abstract: Disclosed is a semiconductor memory device (DRAM) which includes a plurality of island regions, at least one cell transistor disposed on each island region and cylindrical capacitor surrounding said each island region. By so composing, the capacity of the cell capacitor incorporated into a small space can be increased.Also disclosed is method of fabricating a semiconductor memory device which includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane excelling in coverage on it, a step of etching by an etching method having a strong anisotropy in the vertical direction while leaving said deposit membrane on sidewall, and a step of etching deeper the exposed portion of the semiconductor surface in the groove and forming capacity element and isolation region by using this deep trench.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: June 25, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Toshio Yamada, Shinji Odanaka, Masaki Fukumoto
  • Patent number: 5013673
    Abstract: An ion implantation method comprising doping a trench sidewall formed in the surface of a semiconductor substrate, with impurities by intermittently rotating step ion implantation carried out in the state that said sidewall is angled with respect to an ion beam, wherein;the amount of ion implantation to said sidewall is made uniform by varying the scanning velocity of the ion beam on the surface of said semiconductor substrate, at the position near to, and the position distant from, the upstream side of the beam applied to a position at which said surface of semiconductor substrate is inclined with respect to the beam.Also disclosed is a method of manufacturing a semiconductor device making use of such an ion implantation method.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: May 7, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Genshu Fuse
  • Patent number: 4920390
    Abstract: A semiconductor memory device (DRAM) includes a plurality of island regions, at least one cell transistor disposed on each island region and a cylindrical capacitor surrounding each island region. With such a structure, the capacity of the cell capacitor incorporated into a small space can be increased. Furthermore, a method of fabricating a semiconductor memory device includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane having excellent covering characteristics in the groove, a step of etching by using an etching method having a strong anisotropy in the vertical direction while leaving the deposited membrane on a sidewall, and a step of etching the exposed portion of the semiconductor surface deeper in the groove and forming a capacity element and isolation region by using this deep trench.
    Type: Grant
    Filed: July 7, 1988
    Date of Patent: April 24, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Toshio Yamada, Shinji Odanaka, Masaki Fukumoto
  • Patent number: 4918027
    Abstract: A method of fabricating a semiconductor device comprising a step of forming a trench on a semiconductor substrate, a step of positioning the semiconductor substrate in a first position such that the direction of the ion beams is inclined to a plane which is perpendicular to the principal surface of the semiconductor substrate and which is parallel to a first side-wall of the trench, a step of implanting ions into the first side-wall by emitting ion beams onto the first side-wall of the trench of the semiconductor substrate at the first position, a step of rotating the semiconductor substrate about an axis perpendicular to the principal surface thereof to a second position which is different from the first position, a step of implanting ions into a second side-wall by emitting ion beams onto the second side-wall of the trench of the semiconductor substrate at the second position, a step of rotating the semiconductor substrate about the axis to a third position which is different from the first and second posit
    Type: Grant
    Filed: April 27, 1988
    Date of Patent: April 17, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Takashi Ohzone
  • Patent number: 4861729
    Abstract: A method in which in order to dope impurities, with excellent controllability, into a sidewall of a trench formed in a semiconductor substrate, plasma is generated in a gas including the impurities and the semiconductor substrate is disposed in or near the plasma, so that the impurities may be doped into the sidewall of the trench uniformly and at high precision of concentration control; wherein one of a duluted B.sub.2 H.sub.6 gas and diluted AsH.sub.3 gas is chosen as the gas of the plasma, whereby one of B and As as the impurities directly enters the sidewall of the trench without first passing through a film.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: August 29, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Takashi Hirao, Takashi Ohzone
  • Patent number: 4764483
    Abstract: Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.
    Type: Grant
    Filed: August 6, 1987
    Date of Patent: August 16, 1988
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Kenji Tateiwa, Ichiro Nakao, Hideaki Shimoda
  • Patent number: 4487635
    Abstract: A method of producing a superior semiconductor crystallized layer rapidly on a semiconductor substrate with the surface thereof covered with an insulating film is disclosed. An opening, desirably formed by at least two insulating films, is formed at an intersection of scribe lines of the semiconductor substrate. A polycrystal semiconductor film is formed on the insulating films and the opening, after which an energy beam is irradiated spirally on the polycrystal semiconductor film in such a manner that the beam passes at least one opening during each rotation thereof thereby to transform the polycrystal semiconductor film into a crystallized layer for forming a semiconductor element.
    Type: Grant
    Filed: February 14, 1983
    Date of Patent: December 11, 1984
    Assignee: Director-General of the Agency of Industrial Science & Technology
    Inventors: Koichi Kugimiya, Shigenobu Akiyama, Genshu Fuse
  • Patent number: RE37228
    Abstract: A method of fabricating a semiconductor device comprising a step of forming a trench selectively on a semiconductor substrate, a step of positioning said semiconductor substrate to a first position inclined to a plane vertical to ion beams, a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the first position, a step of positioning said semiconductor substrate to a second position which is different from the first position by rotating it, and a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the second position.
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: June 12, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Takashi Ohzone