Patents by Inventor Genzo Monma

Genzo Monma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7018020
    Abstract: A structure is constructed having a through hole in a substrate of silicon or the like by a decreased number of steps in production and with improved reliability. A silicon nitride film is formed in contact with an upper surface of a silicon oxide film at least on a portion of the substrate near the edge of a through hole, thereby improving step coverage of the silicon nitride film. The silicon oxide film and silicon nitride film function as a membrane during formation of the through hole by etching from the back side of the substrate.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: March 28, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yukihiro Hayakawa, Genzo Monma, Masato Kamiichi
  • Publication number: 20030080359
    Abstract: A structure is constructed with a through hole in a substrate of silicon or the like by the decreased number of steps in production and with improved reliability. A silicon nitride film 104 is formed in contact with an upper surface of a silicon oxide film 103 at least in a side portion of a through hole 120, thereby improving step coverage of the silicon nitride film 104. The silicon oxide film 103 and silicon nitride film 104 function as a membrane during formation of the through hole 120 by etching from the back side of substrate 100.
    Type: Application
    Filed: October 16, 2002
    Publication date: May 1, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventors: Yukihiro Hayakawa, Genzo Monma, Masato Kamiichi
  • Patent number: 5918115
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: June 29, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5663099
    Abstract: An alignment method for a semiconductor device having a conductive thin film on a conductive substrate surface across an insulation film, comprises steps of: forming in the insulation film, at least two apertures exposing the substrate surface therein; selectively depositing a conductive material in the apertures thereby forming a stepped portion in at least one of said apertures; and forming the conductive thin film at least on said insulation film. The alignment is conducted utilizing the stepped portion.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: September 2, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiko Okabe, Genzo Monma, Hiroshi Yuzurihara
  • Patent number: 5598037
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: January 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5482893
    Abstract: An alignment method for a semiconductor device having a conductive thin film on a conductive substrate surface across an insulation film, comprises steps of:a) forming in the insulation film, at least two apertures exposing the substrate surface therein;b) selectively depositing a conductive material in the apertures thereby forming a stepped portion in at least one of said apertures; andc) forming the conductive thin film at least on said insulation film. The alignment is conducted utilizing the stepped portion.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: January 9, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiko Okabe, Genzo Monma, Hiroshi Yuzurihara
  • Patent number: 5466961
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: November 14, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5376231
    Abstract: A method for producing a substrate for a recording head wherein a plurality of electro-thermal converting elements, a plurality of driving functional elements for respectively driving the electro-thermal converting elements and a plurality of wiring electrodes for respectively connecting each of the driving functional elements and each of the electro-thermal converting elements are formed on a supporting member by photolithography comprises forming the wiring electrodes by etching a material layer for the wiring electrodes while etchingwise removing a photoresist for masking the material layer for the wiring electrodes.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: December 27, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shigeyuki Matsumoto, Yasuhiro Naruse, Genzo Monma, Kei Fujita, Seiji Kamei, Yutaka Akino, Yasuhiro Sekine, Yukihiro Hayakawa