Abstract: An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

Abstract: A memory access control system is provided between one or more accessing devices and a main memory composed of a plurality of independently accessible logical storages, and receives a request from the accessing device and, based on the status of the main memory, permits access to one of the logical storages. The memory access control system comprises a shift register, composed of stages corresponding to the cycle time of the main memory, for storing address information sufficient for identifying a busy one of the logical storages and for sequentially shifting the stored content in synchronism with a clock signal, and a comparator circuit for comparing the content of each stage of the shift register with address information of the logical storage designated based on the request from the accessing device, receiving the request based on the result of the comparison, and generating a control signal for accessing the designated logical storage.