Patents by Inventor Geo-Myung Shin

Geo-Myung Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159246
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung Il KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Patent number: 10930668
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Publication number: 20200027895
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: February 11, 2019
    Publication date: January 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung II KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Patent number: 9972717
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Patent number: 9847224
    Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyuk Kim, Geo-Myung Shin, Dong-Suk Shin
  • Patent number: 9768300
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9728645
    Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyuk Kim, Geo-Myung Shin, Dong-Suk Shin
  • Publication number: 20170186869
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Application
    Filed: January 13, 2017
    Publication date: June 29, 2017
    Inventors: Dong-Suk SHIN, Hyun-Chul KANG, Dong-Hyun ROH, Pan-Kwi PARK, Geo-Myung SHIN, Nae-In LEE, Chul-Woong LEE, Hoi-Sung CHUNG, Young-Tak KIM
  • Patent number: 9548301
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Publication number: 20160343859
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong JEONG, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Patent number: 9431478
    Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Publication number: 20160247924
    Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Dong-Hyuk KIM, Geo-Myung SHIN, Dong-Suk SHIN
  • Publication number: 20160148930
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Publication number: 20160141381
    Abstract: Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers.
    Type: Application
    Filed: August 3, 2015
    Publication date: May 19, 2016
    Inventors: Kook-Tae KIM, Ho-Sung Son, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Ji-Hye Yi, Sung-Hoon Jung, Yeong-Jong Jeong
  • Patent number: 9337031
    Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyuk Kim, Geo-Myung Shin, Dong-Suk Shin
  • Patent number: 9257520
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Publication number: 20150318399
    Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
    Type: Application
    Filed: January 20, 2015
    Publication date: November 5, 2015
    Inventors: Yeong-Jong JEONG, Jeong-Yun LEE, Geo-Myung SHIN, Dong-Suk SHIN, Si-Hyung LEE, Seo-Jin JEONG
  • Patent number: 9129952
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Publication number: 20150221654
    Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.
    Type: Application
    Filed: October 21, 2014
    Publication date: August 6, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyuk KIM, Geo-Myung SHIN, Dong-Suk SHIN
  • Publication number: 20150214051
    Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: July 30, 2015
    Inventors: Dong-Hyuk KIM, Geo-Myung SHIN, Dong-Suk SHIN