Abstract: Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.

Abstract: An emitter coupled logic (ECL) to transistor-transistor logic (TTL) translator is provided with a transistor clamp operatively coupled in at least one of the alternate transistor collector paths of the ECL input gate for clamping the voltage applied through the transistor collector path by the ECL current source to a level below saturation of the ECL input gate. The source current generated by the ECL current source may therefore be increased for accelerate turn-off of the TTL output gate of the translator without saturation of the ECL input gate. The transistor clamps are also applied in an ECL to tristate TTL translator in which the TTL output gate is a TTL tristate output device or buffer with dual phase splitter transistors. A dual transistor clamp arrangement in at least one of the ECL input gate transistor collector paths also provides separate clamped base drives to the dual phase splitter transistors for eliminating "current hogging" or base drive preemption.

Abstract: A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.