Patents by Inventor Geoff L. Brennecka

Geoff L. Brennecka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10084310
    Abstract: A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 25, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason C. Neely, Joshua Stewart, Jarod James Delhotal, Jack David Flicker, Geoff L. Brennecka