Abstract: A multiplexer (1) having M high frequency input channels (2) and N high frequency output channels (3). The multiplexer (1) comprises N routing control inputs (4); a detector (10) arranged to receive control signals on the or each control input (4), the control signals being indicative of a required connection between the multiplexer input channels (2) and output channels (3); and a decoder (11) arranged to decode the received control signals and generate switching control signals (8) to selectively connect the input channels (2) to the output channels (3) in response to the decoded control signals. The multiplexer (1) is integrated onto a single chip. A multiplexer apparatus comprising a pair of such multiplexers (1) mounted on a printed circuit board is also described. The multiplexers (1) are positioned on opposite sides of the printed circuit board, with one multiplexer (1) rotated 180° about a diagonal axis (20) relative to the other multiplexer (1).