Abstract: An assembly includes optical fibers each having a waveguide core, a photonic integrated circuit (IC) that includes in-plane waveguides corresponding to the optical fibers, and a substrate bonded to the photonic IC with grooves that support the optical fibers. The substrate and photonic IC can have metal bumps that cooperate to provide mechanical bonding and electrical connections between the substrate and photonic IC. Portions of the optical fibers supported by the substrate grooves can define flat surfaces spaced from the optical fiber cores. The photonic IC can include passive waveguide structures with a first coupling section that interfaces to the flat surface of a corresponding optical fiber (for evanescent coupling of optical signals) and a second coupling section that interfaces to a corresponding in-plane waveguide (for adiabatic spot-size conversion of optical signals).

Abstract: A coherent optical receiver that receives an optical PSK-modulated signal includes optical elements that combine the optical PSK-modulated signal and an optical local-oscillating (LO) signal and splits the combined optical signals into multiple parts that have a predefined phase offset relative to one another. The receiver further includes at least one thyristor and control circuitry operably coupled to terminals of the at least one thyristor. The control circuitry is configured to receive the multiple parts of the combined optical signals and controls switching operation of the at least one thyristor according to phase offset of optical PSK-modulated signal relative to the optical LO signal.

Abstract: An optical AND gate is provided that includes an optical thyristor configured to receive first and second digital optical signal inputs. The optical AND gate further includes control circuitry operably coupled to terminals of said optical thyristor. The control circuitry is configured to control switching operation of said optical thyristor in response to the ON/OFF states of the first and second digital optical signal inputs such that the optical thyristor produces a digital output signal that represents the AND function of the first and second digital optical signal inputs. In another aspect, an AND gate is provided that includes a thyristor and control circuitry operably coupled to terminals of the thyristor.

Abstract: An optical XOR circuit that includes a thyristor and control circuitry operably coupled to terminals of the thyristor. The control circuitry is configured to control switching operation of the thyristor in response to the ON/OFF states of two digital optical signal inputs such that the thyristor produces a digital signal output that is the XOR function of the two digital optical signal inputs.

Abstract: An optical phase detector circuit is provided that is suitable for use in an optical phase lock loop. The optical phase detector includes a first optical flip-flop circuit configured to produce a first digital output based on ON/OFF state of a first digital optical input and a digital electrical control signal. A second optical flip-flop circuit is configured to produce a second digital output based on ON/OFF state of a second digital optical input and the digital electrical control signal. An AND gate is operably coupled to both the first and second optical flip-flops. The AND gate produces the digital electrical control signal for supply to the first and second optical flip-flop circuits according to an AND function of the first and second digital outputs produced by the first and second optical flip-flop circuits.

Abstract: An optoelectronic circuit for producing an optical clock signal that includes an optical thyristor, a waveguide structure and control circuitry. The waveguide structure is configured to split an optical pulse produced by the optical thyristor such that a first portion of such optical pulse is output as part of the optical clock signal and a second portion of such optical pulse is guided back to the optical thyristor to produce another optical pulse that is output as part of the optical clock signal. The control circuitry is operably coupled to terminals of the optical thyristor and receives first and second control signal inputs. The control circuitry is configured to selectively decrease frequency of the optical clock signal based on the first control signal input and to selectively increase frequency of the optical clock signal based on the second control signal input.

Abstract: An optical flip-flop circuit that includes an optical thyristor configured to receive a digital optical signal input and produce a digital signal output based on the ON/OFF state of the digital optical signal input. The optical flip-flop circuit further includes control circuitry operably coupled to the terminals of the optical thyristor. The control circuitry is configured to control switching operation of the optical thyristor in response to the level of a digital electrical signal input.

Abstract: A semiconductor device that includes an optical resonator spaced from a waveguide structure to provide for evanescent-wave optical coupling therebetween. The optical resonator includes a closed loop waveguide defined by an epitaxial layer structure that includes at least one quantum well. The semiconductor device also includes circuitry configured to supply an electrical signal that flows within the epitaxial layer structure of the closed loop waveguide. The electrical signal affects charge density in at least quantum well of the closed loop waveguide and controls refractive index of the closed loop waveguide. In one embodiment, the electrical signal is a DC current signal that flows within a vertical thyristor structure of the closed loop waveguide to control refractive index of the closed loop waveguide such that resonance frequency of the closed loop waveguide corresponds to a characteristic wavelength of light.

Abstract: A semiconductor device that includes an optical resonator spaced from a waveguide structure to provide for evanescent-wave optical coupling therebetween. The optical resonator includes a closed loop waveguide defined by a vertical thyristor structure. In one embodiment, the vertical thyristor structure is formed by an epitaxial layer structure including complementary (both an n-type and a p-type) modulation doped quantum well interfaces formed between an N+ region and a P+ region.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.

Abstract: A WDM transmitter and/or receiver optoelectronic integrated circuit includes a plurality of microresonators and corresponding waveguides and couplers that are integrally formed on a substrate. For the WDM transmitter, the microresonators and waveguides are configured to generate a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit one optical signal from one waveguide to the output waveguide such that the plurality of optical signals are multiplexed on the output waveguide. For the WDM receiver, an input waveguide is configured to provide for propagation of a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit at least one optical signal from the input waveguide to one waveguide.

Abstract: A charge pump circuit for an optical phase lock loop, which includes first and second optical thyristors configured to receive respective first and second digital optical signal inputs. A first control circuit receives a first digital electrical signal input corresponding to the second digital optical signal input, and a second control circuit receives a second digital electrical signal input corresponding to the first digital optical signal input. The first control circuitry controls switching operation of the first optical thyristor that sources current to a first filter circuit in response to the levels of the first digital optical signal input and the first digital electrical signal input. The second control circuitry control switching operation of the second optical thyristor that sinks current from a second filter circuit in response to the levels of the second digital optical signal input and the second digital electrical signal input.

Abstract: A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.

Abstract: A photonic analog-to-digital converter is provided that includes a tunable light source, an optical sampling clock source, an optical splitter and a plurality of optical signal processing channels. The tunable light source produces an optical signal at a variable wavelength corresponding to analog levels of an electrical input signal. The optical sampling clock source produces an optical sampling clock signal that defines a sequence of sampling periods. The optical splitter is operably coupled to the tunable light source. The optical splitter splits the optical signal produced by the tunable light source for supply to the plurality of optical signal processing channels. Each one of the optical signal processing channels includes a photonic filter and corresponding optoelectronic thyristor comparator that is operably coupled to the optical sampling clock source.

Abstract: A monolithic semiconductor device that includes a waveguide structure optically coupled to an optical resonator. The optical resonator is adapted to process light at a predetermined wavelength. The optical resonator includes a closed loop waveguide having a plurality of straight sections that are optically coupled together by bend sections.

Abstract: An assembly includes optical fibers each having a waveguide core, a photonic integrated circuit (IC) that includes in-plane waveguides corresponding to the optical fibers, and a substrate bonded to the photonic IC with grooves that support the optical fibers. The substrate and photonic IC can have metal bumps that cooperate to provide mechanical bonding and electrical connections between the substrate and photonic IC. Portions of the optical fibers supported by the substrate grooves can define flat surfaces spaced from the optical fiber cores. The photonic IC can include passive waveguide structures with a first coupling section that interfaces to the flat surface of a corresponding optical fiber (for evanescent coupling of optical signals) and a second coupling section that interfaces to a corresponding in-plane waveguide (for adiabatic spot-size conversion of optical signals).

Abstract: A semiconductor device employs an epitaxial layer arrangement including a first ohmic contact layer and first modulation doped quantum well structure disposed above the first ohmic contact layer. The first ohmic contact layer has a first doping type, and the first modulation doped quantum well structure has a modulation doped layer of a second doping type. At least one isolation ion implant region is provided that extends through the first ohmic contact layer. The at least one isolation ion implant region can include oxygen ions. The at least one isolation ion implant region can define a region that is substantially free of charge carriers in order to reduce a characteristic capacitance of the device. A variety of high performance transistor devices (e.g., HFET and BICFETs) and optoelectronic devices can employ this device structure. Other aspects of wavelength-tunable microresonantors and related semiconductor fabrication methodologies are also described and claimed.

Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).

Abstract: A transistor device is provided that includes a gate electrode disposed between source and drain electrodes and overlying a quantum dot structure realized by a modulation doped quantum well structure. A potential barrier surrounds the quantum dot structure. The transistor device can be configured for operation as a single electron transistor by means for biasing the gate and source electrodes to allow for tunneling of a single electron from the source electrode through the potential barrier surrounding the quantum dot structure and into the quantum dot structure, and means for biasing the gate and drain electrodes to allow for selective tunneling of a single electron from the quantum dot structure through the potential barrier surrounding the quantum dot structure to the drain electrode, wherein the selective tunneling of the single electron is based upon spin state of the single electron.