Patents by Inventor Geoffery L. Reid

Geoffery L. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7057116
    Abstract: An apparatus including a substrate having dimensions suitable as a support circuit for at least one integrated circuit, the substrate comprising a laterally extending plication region defining first and second longitudinal portions; a plurality of conductive traces distributed in a first distribution plane of the substrate and extending transversely through the plication region; a first and second layers of conductive material in a second distribution plane of the first portion and second portion, respectively, of the substrate; at least one conductive bridge extending transversely through less than the entire plication region in the second distribution plane and coupled to the first continuous layer and to the second continuous layer; and at least one externally accessible contact point coupled to at least one of the first and second layers. A method of forming a support circuit and a system including a package.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Geoffery L. Reid, Edward W. Jaeck
  • Publication number: 20040238206
    Abstract: An apparatus including a substrate having dimensions suitable as a support circuit for at least one integrated circuit, the substrate comprising a laterally extending plication region defining first and second longitudinal portions; a plurality of conductive traces distributed in a first distribution plane of the substrate and extending transversely through the plication region; a first and second layers of conductive material in a second distribution plane of the first portion and second portion, respectively, of the substrate; at least one conductive bridge extending transversely through less than the entire plication region in the second distribution plane and coupled to the first continuous layer and to the second continuous layer; and at least one externally accessible contact point coupled to at least one of the first and second layers. A method of forming a support circuit and a system including a package.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventors: Geoffery L. Reid, Edward W. Jaeck
  • Patent number: 6586684
    Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Kristopher Frutschy, Glenn E. Stewart, Farzaneh Yahyaei-Moayyed, Geoffery L. Reid
  • Publication number: 20030000739
    Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Applicant: Intel Corporation
    Inventors: Kristopher Frutschy, Glenn E. Stewart, Farzaneh Yahyaei-Moayyed, Geoffery L. Reid