Patents by Inventor Geoffrey B. Hall
Geoffrey B. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6846717Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.Type: GrantFiled: June 24, 2003Date of Patent: January 25, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Susan H. Downey, James W. Miller, Geoffrey B. Hall
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Patent number: 6724603Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.Type: GrantFiled: August 9, 2002Date of Patent: April 20, 2004Assignee: Motorola, Inc.Inventors: James W. Miller, Geoffrey B. Hall, Alexander Krasin, Michael Stockinger, Matthew D Akers, Vishnu G. Kamat
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Publication number: 20040036174Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.Type: ApplicationFiled: June 24, 2003Publication date: February 26, 2004Inventors: Susan H. Downey, James W. Miller, Geoffrey B. Hall
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Publication number: 20040027742Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.Type: ApplicationFiled: August 9, 2002Publication date: February 12, 2004Inventors: James W. Miller, Geoffrey B. Hall, Alexander Krasin, Michael Stockinger, Matthew D. Akers, Vishnu G. Kamat
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Publication number: 20030173637Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.Type: ApplicationFiled: March 13, 2002Publication date: September 18, 2003Inventors: Susan H. Downey, James W. Miller, Geoffrey B. Hall
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Patent number: 6614091Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.Type: GrantFiled: March 13, 2002Date of Patent: September 2, 2003Assignee: Motorola, Inc.Inventors: Susan H. Downey, James W. Miller, Geoffrey B. Hall
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Publication number: 20020149401Abstract: An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value during at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.Type: ApplicationFiled: April 11, 2001Publication date: October 17, 2002Inventors: Geoffrey B. Hall, Fujio Takeda, Michael Priel
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Patent number: 6459325Abstract: An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.Type: GrantFiled: April 11, 2001Date of Patent: October 1, 2002Assignee: Motorola, Inc.Inventors: Geoffrey B. Hall, Fujio Takeda, Michael Priel
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Patent number: 6351020Abstract: A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate.Type: GrantFiled: November 12, 1999Date of Patent: February 26, 2002Assignee: Motorola, Inc.Inventors: Marc L. Tarabbia, Joseph Y. Chan, Geoffrey B. Hall
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Patent number: 6327126Abstract: A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately ½ of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.Type: GrantFiled: January 28, 2000Date of Patent: December 4, 2001Assignee: Motorola, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Geoffrey B. Hall, Jose A. Camarena, Joseph Chan, Fujio Takeda
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Patent number: 6313664Abstract: A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.Type: GrantFiled: March 20, 2000Date of Patent: November 6, 2001Assignee: Motorola Inc.Inventors: Geoffrey B. Hall, Pedro Ovalle, Dzung T. Tran