Abstract: A method for accelerating machine learning on a computing device is described. The method includes accessing a neural network. The method also includes splitting the neural network into N sub-neural networks. The method further includes hosting the N sub-neural networks in M inference accelerators. The method also includes scheduling the N sub-neural networks in the M inference accelerators. The method further includes executing the N sub-neural networks in the M inference accelerators.

Abstract: A processor-implemented method for a memory storage format to accelerate machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.