Patents by Inventor Geoffrey Gongwer
Geoffrey Gongwer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080019180Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.Type: ApplicationFiled: October 2, 2007Publication date: January 24, 2008Inventors: Jun Wan, Jeffrey Lutze, Masaaki Higashitani, Gerrit Hemink, Ken Oowada, Jian Chen, Geoffrey Gongwer
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Publication number: 20070234144Abstract: A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.Type: ApplicationFiled: June 7, 2007Publication date: October 4, 2007Inventors: Geoffrey Gongwer, Daniel Guterman, Yupin Fong
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Publication number: 20070226434Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.Type: ApplicationFiled: May 22, 2007Publication date: September 27, 2007Inventors: Daniel Guterman, Stephen Gross, Shahzad Khalid, Geoffrey Gongwer
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Publication number: 20070217259Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.Type: ApplicationFiled: May 22, 2007Publication date: September 20, 2007Inventors: Daniel Guterman, Stephen Gross, Shahzad Khalid, Geoffrey Gongwer
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Publication number: 20070150644Abstract: A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Yosi Pinto, Geoffrey Gongwer, Oren Honen
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Publication number: 20070147168Abstract: A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Yosi Pinto, Geoffrey Gongwer, Oren Honen
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Publication number: 20070091681Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: ApplicationFiled: November 21, 2006Publication date: April 26, 2007Inventors: Geoffrey Gongwer, Daniel Guterman
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Publication number: 20070002633Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: ApplicationFiled: September 11, 2006Publication date: January 4, 2007Inventors: Geoffrey Gongwer, Daniel Guterman
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Publication number: 20060279990Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.Type: ApplicationFiled: May 12, 2005Publication date: December 14, 2006Inventors: Jun Wan, Jeffrey Lutze, Masaaki Higashitani, Gerrit Hemink, Ken Oowada, Jian Chen, Geoffrey Gongwer
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Patent number: 7139465Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: GrantFiled: May 9, 2005Date of Patent: November 21, 2006Assignee: SanDisk CorporationInventors: Geoffrey Gongwer, Daniel C. Guterman
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Publication number: 20060239079Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.Type: ApplicationFiled: June 23, 2006Publication date: October 26, 2006Inventors: Nima Mokhlesi, Daniel Guterman, Geoffrey Gongwer
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Publication number: 20060107136Abstract: The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase.Type: ApplicationFiled: December 14, 2005Publication date: May 18, 2006Inventors: Geoffrey Gongwer, Daniel Guterman, Yupin Fong
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Publication number: 20060015677Abstract: Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format.Type: ApplicationFiled: August 9, 2005Publication date: January 19, 2006Inventors: Geoffrey Gongwer, Stephen Gross
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Publication number: 20050213361Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: ApplicationFiled: May 9, 2005Publication date: September 29, 2005Inventors: Geoffrey Gongwer, Daniel Guterman
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Publication number: 20050169051Abstract: The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset.Type: ApplicationFiled: February 22, 2005Publication date: August 4, 2005Inventors: Shahzad Khalid, Daniel Guterman, Geoffrey Gongwer, Richard Simko, Kevin Conley
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Publication number: 20050057979Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.Type: ApplicationFiled: October 28, 2004Publication date: March 17, 2005Inventors: Nima Mokhlesi, Daniel Guterman, Geoffrey Gongwer
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Publication number: 20040174744Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: ApplicationFiled: March 19, 2004Publication date: September 9, 2004Inventors: Geoffrey Gongwer, Daniel C. Guterman
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Patent number: 6738289Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: GrantFiled: February 26, 2001Date of Patent: May 18, 2004Assignee: SanDisk CorporationInventors: Geoffrey Gongwer, Daniel C. Guterman
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Publication number: 20020118574Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.Type: ApplicationFiled: February 26, 2001Publication date: August 29, 2002Inventors: Geoffrey Gongwer, Daniel C. Guterman