Abstract: A method and apparatus for configuring a memory device, such as a flash memory device, is herein described. Features/functional modules of a memory device, are selectable by a manufacturer, customer, or user. Instead of a manufacturer having to complete numerous redesigns of a memory product to meet multiple customer's special needs, a single all inclusive device is manufactured and the customized features are selected/configured, by the manufacturer, or by the customer themselves. By using one time programmable (OTP) flags, the features are enabled or disabled, by the manufacturer, customer, or user, and may potentially not be altered by a user later. Moreover, after configuring a memory device, a manufacturer, customer, or end user may also lock down a configuration module to ensure the configuration itself is not later intentionally or inadvertently altered.

Abstract: Highly effective carbon fibre-reinforced ceramic automotive brake and clutch discs are manufactured by siliconising incompletely densified carbon-carbon fibre preforms produced by a single stage and relatively short duration (e.g. 7-14 day) chemical vapour infiltration process.

Abstract: An apparatus, system, and method for a data invalid signal for non-deterministic latency in memory are described. The apparatus may include a memory to determine that data to be buffered for a data burst cannot be guaranteed in time to satisfy a deterministic latency parameter. The memory may provide an indication that the data cannot be guaranteed. Other embodiments are described and claimed.

Abstract: In accordance with a universal nonvolatile memory boot mode, one or more portions of boot code are obtained from a nonvolatile memory component. These one or more portions are obtained without knowing a row size used by the nonvolatile memory component, a column address strobe (CAS) latency used by the nonvolatile memory component, or a default burst length used by the nonvolatile memory component. The one or more portions of boot code are executed to configure the system to access a volatile memory component, and/or to reconfigure the system to access the nonvolatile memory in a different mode of operation.

Abstract: A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the memory controller. At least one of the physical address pins, which is to be mapped in a time phase in a baseline design, is to be unmapped in a corresponding time phase if a dimensional parameter of the memory changes. The logical address comprises row address bits and column address bits. All of the even row address bits may be mapped in a time phase for outputting the row address, and all of the odd row address bits may be mapped in another time phase for outputting the row address. Thus, configuration flexibility of the memory controller is improved.

Abstract: An apparatus, system, and method for a data invalid signal for non-deterministic latency in memory are described. The apparatus may include a memory to determine that data to be buffered for a data burst cannot be guaranteed in time to satisfy a deterministic latency parameter. The memory may provide an indication that the data cannot be guaranteed. Other embodiments are described and claimed.

Abstract: A method and apparatus for configuring a memory device, such as a flash memory device, is herein described. Features/functional modules of a memory device, are selectable by a manufacturer, customer, or user. Instead of a manufacturer having to complete numerous redesigns of a memory product to meet multiple customer's special needs, a single all inclusive device is manufactured and the customized features are selected/configured, by the manufacturer, or by the customer themselves. By using one time programmable (OTP) flags, the features are enabled or disabled, by the manufacturer, customer, or user, and may potentially not be altered by a user later. Moreover, after configuring a memory device, a manufacturer, customer, or end user may also lock down a configuration module to ensure the configuration itself is not later intentionally or inadvertently altered.

Abstract: A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the memory controller. At least one of the physical address pins, which is to be mapped in a time phase in a baseline design, is to be unmapped in a corresponding time phase if a dimensional parameter of the memory changes. The logical address comprises row address bits and column address bits. All of the even row address bits may be mapped in a time phase for outputting the row address, and all of the odd row address bits may be mapped in another time phase for outputting the row address. Thus, configuration flexibility of the memory controller is improved.

Abstract: Described herein are one or more implementations that eliminate the need to switch data-resource access-modes of a flash memory system between a primary main array memory and a secondary supernumerary data resource. The one or more described implementations provide access to the secondary supernumerary data resource through an overlay window in the addressable memory space of primary main array memory. Memory accesses (e.g., reads or writes) which specify a memory location which is within the defined address space of the overlay window are redirected to the secondary supernumerary data resource instead of accessing the primary main array memory.

Abstract: In accordance with a universal nonvolatile memory boot mode, one or more portions of boot code are obtained from a nonvolatile memory component. These one or more portions are obtained without knowing a row size used by the nonvolatile memory component, a column address strobe (CAS) latency used by the nonvolatile memory component, or a default burst length used by the nonvolatile memory component. The one or more portions of boot code are executed to configure the system to access a volatile memory component, and/or to reconfigure the system to access the nonvolatile memory in a different mode of operation.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to avoid incoherency between a cache memory and a flash memory is provided. The method may include invalidating at least one cache line of information stored in the cache memory to avoid incoherency between the cache memory and the flash memory in response to a flash erase operation, a flash write operation, an operation that makes information inaccessible in the flash memory, or an operation that moves information from one region of the flash memory to another region of the flash memory. Other embodiments are described and claimed.

Abstract: In one embodiment of the present invention, a method includes manipulating a first data image into a modified data image, where the modified data image has a faster write time than the first data image for a memory. The manipulation may be based on an algorithm selected on a priori knowledge of at least one characteristic of the memory or transmission channel to which the modified data is to be sent.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may include a processor coupled to a non-volatile memory device. The non-volatile device may be adapted to monitor system signals and determine if the non-volatile memory device should suspend a current operation.

Abstract: A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block.

Abstract: A method of preconditioning a nonvolatile memory array including a first memory cell and a second memory cell. Preconditioning begins by applying an initial precondition pulse to all memory cells in the nonvolatile memory array without pausing to perform precondition verification. After this first step, precondition verification begins. The voltage level of the first memory cell is sensed and compared to a selected voltage level. If the threshold voltage of the first memory cell is below the selected voltage, the first memory cell did not precondition verify. In that case, another precondition pulse is then applied to the first memory cell. Application of precondition pulses and precondition verification continues until the first memory cell verifies as preconditioned. Attention turns to the second memory cell after the first memory cell precondition verifies. If the second memory cell does not precondition verify another precondition pulse is applied to the second memory cell.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.