Patents by Inventor Geoffrey L. Thiel

Geoffrey L. Thiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020093590
    Abstract: Apparatus for synchronising a plurality of independent video signal generators comprises a first input (12) for receiving field or frame synchronising signals from a first video signal generator, a second input (14) for receiving field or frame synchronising signals from a second video signal generator, a comparator (13) for comparing the phase of the first and second synchronisation signals, a master clock generator (1), a slave clock generator (4), the slave clock generator (4) having a frequency different from that of the master clock generator (1), means for applying the master clock signal to a first output (7) for application to the first video signal generator, means for applying the slave clock signal to a second output (9) for application to the second video signal generator, and means (5) for means for applying the master clock signal to the second output (9) in place of the slave clock signal when the synchronising signals from the first and second synchronising signals are in phase.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 18, 2002
    Inventors: Douglas H. Hodgkiss, Geoffrey L. Thiel
  • Patent number: 5586256
    Abstract: A computer system includes sixteen data processors each connected to a communication bus. The communication bus comprises a data bus for carrying data, and an address bus for carrying associated labelling information uniquely identifying the data. Each processor includes read and write detectors connected to the address bus for detecting labelling information of data required by, or presently stored in, respectively, the data processor. A bulk memory having similar read and write detectors is connected to the communication bus. An address generator supplies labelling addresses to the address bus. For each address, one processor or the bulk memory supplies the corresponding data to the data bus, and other processors and/or the bulk memory requiring the data read the data from the data bus. Data is transferred between processors and/or the bulk memory in this way. The address bus and the read and write decoders are configured for multi-dimensional addressing.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: December 17, 1996
    Assignee: Akebia Limited
    Inventors: Geoffrey L. Thiel, Paul S. Pontin
  • Patent number: 4887211
    Abstract: An apparatus for processing image data of a computerized tomography system having image data acquisition and main storage devices is provided. The image processing apparatus includes an image processor memory for storing image data and a plurality of operation means having processing apparatus for sequentially performing processing operations on the image data. The apparatus further includes a process controller for providing the image processor memory and the operation means with control data specifying the processing operations to be sequentially performed by the plurality of operation means and for generating sequence selection data. The apparatus also includes a sequencer means for selecting the sequence in which the processing operations are to be performed in accordance with the sequence selection data.
    Type: Grant
    Filed: November 25, 1986
    Date of Patent: December 12, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Geoffrey L. Thiel, Douglas H. Hodgkiss, Hisanori Tohara
  • Patent number: 4884196
    Abstract: A system for sequentially providing external circuit data for an external circuit comprising: a memory having a plurality of memory locations identified by addresses, each memory location containing an instruction comprising external circuit data and memory location data, the memory further comprising an address input terminal for currently accessing one of the memory locations in response to receipt of the address for that memory location at the address input terminal; a sequencer, coupled to the memory to receive memory location data from the currently addressed one of the memory locations, for selecting the address of another of the memory locations in response to the next memory location data; a first register, coupled between the sequencer and the address input terminal of the memory to receive the address of the other of the memory locations from the sequencer for storing the address selected by the sequencer to make the address available at the address input terminal of the memory to access the other o
    Type: Grant
    Filed: October 6, 1986
    Date of Patent: November 28, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Geoffrey L. Thiel, Douglas H. Hodgkiss, Hisanori Tohara
  • Patent number: 4827413
    Abstract: A method for displaying three dimensional imaging system data uses a modified Back To Front algorithm. With that algorithm, imaging system data are interpolated and converted into a series of vectors defined by a starting point in space and a length corresponding to consecutive non-zero imaging system data points. The vectors are transformed to an observer's viewpoint coordinate system and plotted on a CRT display.
    Type: Grant
    Filed: June 16, 1987
    Date of Patent: May 2, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: David R. Baldwin, Geoffrey L. Thiel