Patents by Inventor Geoffrey N. Ellis
Geoffrey N. Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12136000Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.Type: GrantFiled: April 20, 2023Date of Patent: November 5, 2024Assignee: Coherent Logix, IncorporatedInventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
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Publication number: 20230359509Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.Type: ApplicationFiled: April 20, 2023Publication date: November 9, 2023Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
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Publication number: 20230359548Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: ApplicationFiled: June 15, 2023Publication date: November 9, 2023Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Patent number: 11755382Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.Type: GrantFiled: November 1, 2018Date of Patent: September 12, 2023Assignee: Coherent Logix, IncorporatedInventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
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Patent number: 11720479Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: GrantFiled: October 17, 2018Date of Patent: August 8, 2023Assignee: Coherent Logix, IncorporatedInventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Publication number: 20190138365Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.Type: ApplicationFiled: November 1, 2018Publication date: May 9, 2019Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
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Publication number: 20190050324Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Patent number: 10114739Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: GrantFiled: September 26, 2016Date of Patent: October 30, 2018Assignee: Coherent Logix, IncorporatedInventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Publication number: 20170010958Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Patent number: 9477585Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: GrantFiled: November 8, 2013Date of Patent: October 25, 2016Assignee: COHERENT LOGIX, INCORPORATEDInventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Publication number: 20140137082Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: ApplicationFiled: November 8, 2013Publication date: May 15, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio