Patents by Inventor Geoffrey N. Ellis

Geoffrey N. Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12136000
    Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: November 5, 2024
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
  • Publication number: 20230359509
    Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
    Type: Application
    Filed: April 20, 2023
    Publication date: November 9, 2023
    Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
  • Publication number: 20230359548
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Application
    Filed: June 15, 2023
    Publication date: November 9, 2023
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 11755382
    Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 12, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
  • Patent number: 11720479
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 8, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Publication number: 20190138365
    Abstract: Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 9, 2019
    Inventors: Michael L. Purnell, Geoffrey N. Ellis, Teng-I Wang
  • Publication number: 20190050324
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 10114739
    Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Publication number: 20170010958
    Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Patent number: 9477585
    Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 25, 2016
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
  • Publication number: 20140137082
    Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 15, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio