Abstract: A digital processor system including several function modules where each modules includes circuitry to perform at least one computational task and circuitry to transfer information containing that module's respective computational task capability to a logical arbiter upon initialization. Each module further includes circuitry to interface to the logical arbiter upon initialization to determine that module's address. Further disclosed is an information bus that connects all function modules together with the logical arbiter. The presence of the logical arbiter provides for a self-configuration capability upon initialization.

Abstract: A digital processor system including several function modules where each module includes circuitry to perform at least one computational task and the circuitry to transfer information containing that modules respective computational task capability to a global memory upon initialization of each module and further circuitry to interface to the global memory upon initialization together with circuitry to interface to the global memory to determine each modules address. Further included is an information bus connected to the function modules and the to global memory. This system configuration allows for the system to self-configure upon power up intialization.