Patents by Inventor Geoffrey Pourtois
Geoffrey Pourtois has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230382756Abstract: A mixed metal oxide and methods for making the mixed metal oxide are disclosed. The mixed metal oxide includes metal and metalloid elements including 0.40 to 0.70 parts by mole Mg, 0.30 to 0.60 parts by mole Zn, and 0.00 to 0.30 parts by mole of other elements selected from metals and metalloids, wherein less than 0.01 parts by mole of the other elements is Al, and wherein less than 0.04 parts by mole of the other elements is Ga. The sum of all parts by mole of Mg, Zn, and the other elements may amount to about 1.00. The mixed metal oxide additionally includes) oxygen and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: May 26, 2023Publication date: November 30, 2023Inventors: Michiel Jan Van Setten, Geoffrey Pourtois, Hendrik F.W. Dekkers, Gouri Sankar Kar
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Publication number: 20230382758Abstract: Mixed metal oxides and methods for making the mixed metal oxides are disclosed. A mixed metal oxide includes metal or metalloid elements including 0.50 to 0.90 parts by mole Mg, 0.05 to 0.30 parts by mole Al, 0.01 to 0.20 parts by mole Sb, and 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids. The sum of all parts by mole of Mg, Al, Sb, and the other elements selected from metals and metalloids may amount to about 1.00. The mixed metal oxide additionally includes oxygen, and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: May 30, 2023Publication date: November 30, 2023Inventors: Michiel Jan van Setten, Geoffrey Pourtois, Hendrik F.W. Dekkers, Gouri Sankar Kar
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Publication number: 20230010899Abstract: In an aspect, a mixed metal oxide comprises or consists essentially of: a mixture comprises or consisting essentially of 0.30 to 0.69 parts by mole Mg, 0.20 to 0.69 parts by mole Zn, 0.01 to 0.30 parts by mole of a third element selected from Al and Ga, and, either, when the third element is Al, 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids, or, when the third element is Ga, 0.00 to 0.15 parts by mole of other elements selected from metals and metalloids, wherein the sum of all parts by mole of Mg, Zn, the third element, and the other elements amounts to 1.00, wherein the amount in parts by mole of the other elements is lower than the amount in parts by mole of Mg and is lower than the amount in parts by mole of Zn; oxygen; and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: July 1, 2022Publication date: January 12, 2023Inventors: Michiel Jan van Setten, Hendrik F.W Dekkers, Karl Opsomer, Geoffrey Pourtois, Gouri Sankar Kar
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Patent number: 11387350Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.Type: GrantFiled: December 18, 2019Date of Patent: July 12, 2022Assignee: IMEC vzwInventors: Geert Eneman, Bartlomiej Pawlak, Liesbeth Witters, Geoffrey Pourtois
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Publication number: 20200212205Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.Type: ApplicationFiled: December 18, 2019Publication date: July 2, 2020Inventors: Geert Eneman, Bartlomiej PAWLAK, Liesbeth WITTERS, Geoffrey POURTOIS
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Publication number: 20190067564Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer comprising CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer comprising MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.Type: ApplicationFiled: August 13, 2018Publication date: February 28, 2019Inventors: Johan Swerts, Kiroubanand Sankaran, Tsann Lin, Geoffrey Pourtois
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Patent number: 10128338Abstract: Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material.Type: GrantFiled: October 18, 2017Date of Patent: November 13, 2018Assignee: IMEC VZWInventors: Hao Yu, Geoffrey Pourtois
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Patent number: 10050192Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer including CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer including MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.Type: GrantFiled: December 8, 2016Date of Patent: August 14, 2018Assignee: IMEC vzwInventors: Johan Swerts, Kiroubanand Sankaran, Tsann Lin, Geoffrey Pourtois
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Patent number: 9982360Abstract: A method for transferring a graphene layer from a metal substrate to a second substrate is provided comprising: providing a graphene layer on the metal substrate, adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer, treating the metal substrate having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate, transferring the graphene layer to the second substrate, and optionally reusing the metal substrate by repeating the aforementioned steps.Type: GrantFiled: September 15, 2014Date of Patent: May 29, 2018Assignee: IMEC VZWInventors: Cedric Huyghebaert, Philippe M. Vereecken, Geoffrey Pourtois
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Patent number: 9979402Abstract: The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone.Type: GrantFiled: May 3, 2017Date of Patent: May 22, 2018Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Adrien Vaysset, Iuliana Radu, Geoffrey Pourtois
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Publication number: 20180108734Abstract: Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material.Type: ApplicationFiled: October 18, 2017Publication date: April 19, 2018Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Hao Yu, Geoffrey Pourtois
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Patent number: 9899501Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.Type: GrantFiled: December 15, 2016Date of Patent: February 20, 2018Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Geoffrey Pourtois, Anh Khoa Lu, Cedric Huyghebaert
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Publication number: 20170302280Abstract: The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone.Type: ApplicationFiled: May 3, 2017Publication date: October 19, 2017Inventors: Adrien Vaysset, luliana Radu, Geoffrey Pourtois
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Publication number: 20170179263Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.Type: ApplicationFiled: December 15, 2016Publication date: June 22, 2017Inventors: Geoffrey Pourtois, Anh Khoa Lu, Cedric Huyghebaert
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Publication number: 20170170390Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer comprising CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer comprising MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.Type: ApplicationFiled: December 8, 2016Publication date: June 15, 2017Inventors: Johan Swerts, Kiroubanand Sankaran, Tsann Lin, Geoffrey Pourtois
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Patent number: 9608094Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.Type: GrantFiled: August 31, 2015Date of Patent: March 28, 2017Assignee: IMEC VZWInventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
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Patent number: 9431519Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.Type: GrantFiled: May 22, 2015Date of Patent: August 30, 2016Assignees: IMEC VZW, Sony CorporationInventors: Hideki Minari, Shinichi Yoshida, Geoffrey Pourtois, Matty Caymax, Eddy Simoen
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Patent number: 9281040Abstract: A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.Type: GrantFiled: December 4, 2013Date of Patent: March 8, 2016Assignee: IMECInventors: Bart Soree, Marc Heyns, Geoffrey Pourtois
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Publication number: 20160064535Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.Type: ApplicationFiled: August 31, 2015Publication date: March 3, 2016Inventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
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Publication number: 20150340503Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.Type: ApplicationFiled: May 22, 2015Publication date: November 26, 2015Applicants: SONY CORPORATION, IMEC VZWInventors: Hideki Minari, Shinichi Yoshida, Geoffrey Pourtois, Matty Caymax, Eddy Simoen