Abstract: Improved wavelength division multiplexed optical links and signal processing methods that employ cross tap equalization to reduce crosstalk arising from inadequate optical filtering. After optical filtering and photodetection, the wavelength division multiplexed signals adjacent either side of a signal whose crosstalk is to be reduced are sampled, weighted and are then subtracted from the signal whose crosstalk is to be reduced. This is done using adaptive correlation, performed simultaneously on all signals, each with respect to its respective adjacent channels. The present invention enables more closely spaced optical carriers to be used in the wavelength division multiplexed optical link.

Abstract: A system for processing inphase and quadrature data channels, such as a Costas loop QPSK demodulator, employs an additional feedback loop for adjustment of phase offset between carrier reference signals, this loop being in addition to the Costas error loop for control of frequency and phase of an oscillator which provides the regenerated carrier signal. The additional loop employs cross-channel products of demodulated inphase and quadrature data signals as does the Costas loop. The regenerated carrier is applied via an adjustable phase-offset unit to provide quadrature carrier reference signals to phase detectors of inphase and quadrature data channels. The phase offset unit includes a 90 degree hybrid circuit energized by the carrier signal at a main input port plus an adjustable fraction of the carrier power applied to an auxiliary input port.

Abstract: An equalizer (10) for removing parabolic phase distortion from an analog signal (3), utilizing a pair of series connected transversal filters. The parabolic phase distortion is cancelled by generating an inverse parabolic approximation using a sinusoidal phase control filter (18). The signal (3) is then passed through an amplitude control filter (21) to remove magnitude ripple components.

Abstract: A lock detector circuit (60) for demodulators of UQPSK signals I and Q has signal processing circuits for forming the signals:A=6I.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4 ;B=4(I.sup.2 -Q.sup.2).A switch (19) is provided for coupling either signal A or signal B to the output (20) of the detector circuit, depending on the value of the signal ratio Q/I. In an alternative embodiment, a summing circuit adds signal A and signal B, and directs the sum to the detector output (20). The resulting output signal is constant under lock conditions, and oscillates when the demodulator is unlocked. This output signal is directed through a comparator (49) to the sweep circuit (43) controlling demodulator VCO (42), and causes the demodulator to remain in the locked condition. The lock detector circuit is effective for any value of Q/I, and utilizes only three analog multiplier circuits.