Abstract: For weighting input signal in accordance with a mathematical transfer function represented by a plurality of straight lines each of which intersects the next at a separate break-point, signal processing apparatus receives or generates a train of pulses, the number of pulses received over a sampling period being related to the signal, and detects preset numbers of pulses corresponding to the break-points, the number detected at the end of the sampling period identifying the highest break-point reached. The detection of each break-point is used to produce an analogue signal corresponding to the value of the break-point and a voltage source is selected corresponding to the gradient of the straight line section following the break-point. Pulses received after each break-point are counted, to be re-set at the next break-point, and the total at the end of the sampling period multiplied by the gradient in a D/A converter to give the analogue value of the signal in excess of the highest break-point.

Abstract: A frequency sensitive switching arrangement is arranged to cause a bistable switching arrangement to produce an output signal at a first or second level depending whether the pulse rate is below a lower rate or above a higher rate with hysteresis preventing change of level between the rates. The bistable switch is arranged to give an output signal at a first or second level in dependence on whether an input pulse is applied to a first or second input. A first monostable element having a first preset unstable period opens a gate to permit pulses to be applied to the second input for the first unstable period and a second monostable element having a second preset unstable period, longer than the first, closes a gate to prevent pulses from being applied to the first input terminal for the second unstable period. Any input pulses occurring between the end of first and second periods is not applied to either terminal and the output level remains as previously.

Abstract: A circuit arrangement for indicating when the pulse repetition frequencies of two pulse trains differ by a predetermined amount comprises a multi-stage shift register containing a binary digit in one of the central stages, pulses from each train are applied to the register alternately by means of clock pulses and individual pulses of each train cause the binary digit to be moved through one stage but in opposite senses. While the repetition frequencies are equal the binary digit oscillates between two stages but if unequal numbers of pulses are received in each train then the binary digit migrates along the stages of the register. An output signal is derived from stages of the register displaced by a predetermined number from the central stages. The circuit is reset after a predetermined number of input pulses so that the percentage difference between the two repetition frequencies is indicated.