Abstract: Single-shot learning and disambiguation of multiple predictions in hierarchical temporal memory is provided. In various embodiments an input sequence is read. The sequence comprises first, second, and third time-ordered components. Each of the time-ordered components is encoded in a sparse distributed representation. The sparse distributed representation of the first time-ordered component is inputted into a first portion of a hierarchical temporal memory. The sparse distributed representation of the second time-ordered component is inputted into a second portion of the hierarchical temporal memory. The second portion is connected to the first portion by a first plurality of synapses. A plurality of predictions as to the third time-ordered component is generated within a third portion of the hierarchical temporal memory. The third portion is connected to the second portion by a second plurality of synapses.

Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.

Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.

Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract: A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.

Abstract: Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from the top contact towards the main body. A minimum width of the channel has a less than minimum lithographic dimension and is narrower than a width of the main body. Therefore, the channel provides a confined region for the switching current path and restricts phase changing to within the channel. In addition an embodiment of the memory cell isolates the main body of phase change material by providing a space between the phase change material and the cell walls. The space allows the phase change material to expand and contract and also limits heat dissipation.

Abstract: A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thing films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract: A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.

Abstract: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.