Patents by Inventor Geoffrey Zhang
Geoffrey Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127683Abstract: In an example method, a mobile device obtains a signal indicating an acceleration measured by a sensor over a time period. The mobile device determines an impact experienced by the user based on the signal. The mobile device also determines, based on the signal, one or more first motion characteristics of the user during a time prior to the impact, and one or more second motion characteristics of the user during a time after the impact. The mobile device determines that the user has fallen based on the impact, the one or more first motion characteristics of the user, and the one or more second motion characteristics of the user, and in response, generates a notification indicating that the user has fallen.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Inventors: Xing Tan, Huayu Ding, Parisa Dehleh Hossein Zadeh, Harshavardhan Mylapilli, Hung A. Pham, Karthik Jayaraman Raghuram, Yann Jerome Julien Renard, Sheena Sharma, Alexander Singh Alvarado, Umamahesh Srinivas, Xiaoyuan Tu, Hengliang Zhang, Geoffrey Louis Chi-Johnston, Vivek Garg
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Publication number: 20240111291Abstract: Building infrastructure and robot coordination methods and systems are disclosed herein. An example method can include preregistering an autonomous vehicle with a building controller of a building to inform the building controller of arrival of the autonomous vehicle and a delivery request for a package, the delivery request specifying a recipient of the package, the recipient having a location in the building. The method can include determining completion of a validation routine with the autonomous vehicle, assigning a task management plan to the autonomous vehicle, the task management plan determining how the autonomous vehicle navigates through the building to deliver the package to the location, and tracking the autonomous vehicle through the building.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Ford Global Technologies, LLCInventors: Geoffrey Horowitz, Yifan Chen, Sarah Garrow, Gregory Linkowski, Meghna Menon, Songan Zhang
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Patent number: 11944393Abstract: Disclosed herein are a surgical system for patella tracking and a method for selecting a properly-sized patellar implant utilizing the same. The surgical system may include first and second trackers and a patellar tracking system. The first tracker may be configured to contact an unresected or a resected patella, and the second tracker may be configured to contact a bone. The patellar tracking system may be configured to track the first and second trackers during patellar flexion and extension to generate patellar range of motion and patellar trial range of motion. A method for selecting a patellar implant may utilize the first and second trackers and the patellar tracking system.Type: GrantFiled: October 27, 2022Date of Patent: April 2, 2024Assignee: Mako Surgical Corp.Inventors: Daniel Antonio Perez, Daniel Rudolf Scholl, Gokce Yildirim, Alvin Perez, Alex McLachlan, Zenan Zhang, Geoffrey Westrich
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Publication number: 20240006565Abstract: A light-emitting module includes a carrier circuit board, a light-blocking wall, a light conversion medium layer, and multiple light-emitting chips. The multiple light-emitting chips are packaged on the carrier circuit board, and each light-emitting chip is configured to emit first color light. The light-blocking wall is on the carrier circuit board and surrounds the multiple light-emitting chips. The light conversion medium layer covers the multiple light-emitting chips and part of the carrier circuit board in a space enclosed by the light-blocking wall. The light conversion medium layer is configured to convert the first color light emitted by the light-emitting chips into second color light.Type: ApplicationFiled: June 30, 2023Publication date: January 4, 2024Inventors: Geoffrey Zhang, Terry Huang
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Patent number: 11522735Abstract: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.Type: GrantFiled: August 20, 2020Date of Patent: December 6, 2022Assignee: XILINX, INC.Inventors: Kevin Zheng, Hongtao Zhang, Geoffrey Zhang
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Patent number: 11423303Abstract: Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.Type: GrantFiled: November 21, 2019Date of Patent: August 23, 2022Assignee: XILINX, INC.Inventors: Shuo Jiao, Romi Mayder, Bowen Li, Geoffrey Zhang
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Patent number: 11038768Abstract: A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.Type: GrantFiled: September 15, 2016Date of Patent: June 15, 2021Assignee: XILINX, INC.Inventors: Ivan O. Madrigal, Michael O. Jenkins, Hong S. Ahn, Murtuza Z. Cutleriwala, Alan C. Wong, Christopher J. Borrelli, Yohan Frans, Geoffrey Zhang, Hongtao Zhang
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Patent number: 10644844Abstract: A circuit for determining data error spacing in a data transmitter is disclosed. The circuit comprises a counter; encoding logic configured to receive an output of the counter, wherein the encoding circuit enables generating error spacing information; and a storage element configured to receive an output of the encoding logic.Type: GrantFiled: April 5, 2017Date of Patent: May 5, 2020Assignee: Xilinx, Inc.Inventors: Winson Lin, Hongtao Zhang, Yu Xu, Geoffrey Zhang
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Patent number: 10530561Abstract: Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference en to a predetermined stability criteria T1 of the receiver. The moving average difference en may include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter un of the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.Type: GrantFiled: March 20, 2019Date of Patent: January 7, 2020Inventors: Zao Liu, Yang Liu, Zhaoyin D. Wu, Geoffrey Zhang, Yu Xu, Alan C. Wong
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Patent number: 10404445Abstract: A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.Type: GrantFiled: July 3, 2018Date of Patent: September 3, 2019Assignee: XILINX, INC.Inventors: Hongtao Zhang, Jinyung NamKoong, Winson Lin, Yohan Frans, Geoffrey Zhang
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Patent number: 10404408Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.Type: GrantFiled: December 13, 2016Date of Patent: September 3, 2019Assignee: XILINX, INC.Inventors: Winson Lin, Hongtao Zhang, Yu Xu, Geoffrey Zhang
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Patent number: 10367666Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.Type: GrantFiled: March 28, 2017Date of Patent: July 30, 2019Assignee: XILINX, INC.Inventors: Hongtao Zhang, Yohan Frans, Geoffrey Zhang
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Patent number: 10291239Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.Type: GrantFiled: June 5, 2018Date of Patent: May 14, 2019Assignee: XILINX, INC.Inventors: Zhaoyin D. Wu, Winson Lin, Parag Upadhyaya, Geoffrey Zhang, Kun-Yung Chang
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Patent number: 10256968Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.Type: GrantFiled: July 26, 2017Date of Patent: April 9, 2019Assignee: XILINX, INC.Inventors: Zhaoyin D. Wu, Yu Xu, Winson Lin, Yohan Frans, Geoffrey Zhang
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Patent number: 10224937Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.Type: GrantFiled: April 20, 2018Date of Patent: March 5, 2019Assignee: XILINX, INC.Inventors: Zhaoyin D. Wu, Geoffrey Zhang, Parag Upadhyaya, Kun-Yung Chang
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Publication number: 20180287837Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: Xilinx, Inc.Inventors: Hongtao Zhang, Yohan Frans, Geoffrey Zhang
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Patent number: 10038545Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.Type: GrantFiled: July 26, 2017Date of Patent: July 31, 2018Assignee: XILINX, INC.Inventors: Zhaoyin D. Wu, Winson Lin, Yu Xu, Geoffrey Zhang
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Patent number: 9882795Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.Type: GrantFiled: April 17, 2015Date of Patent: January 30, 2018Assignee: XILINX, INC.Inventors: Hongtao Zhang, Geoffrey Zhang, Yu Xu, Patrick Satarzadeh, Zhaoyin D. Wu
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Patent number: 9800438Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.Type: GrantFiled: October 25, 2016Date of Patent: October 24, 2017Assignee: XILINX, INC.Inventors: Hongtao Zhang, Zhaoyin D. Wu, Christopher J. Borrelli, Geoffrey Zhang
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Patent number: 9654327Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.Type: GrantFiled: May 27, 2015Date of Patent: May 16, 2017Assignee: XILINX, INC.Inventors: Yu Liao, Geoffrey Zhang, Hongtao Zhang, Kun-Yung Chang, Toan Pham, Zhaoyin D. Wu