Patents by Inventor Geol NAM
Geol NAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145437Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
-
Publication number: 20240118196Abstract: In the case of a gas in which several gases are mixed, a type and concentration of the gas may be incorrectly measured when measured using only an optical band-pass filter. The invention of the present application is directed to providing a technology in which a plurality of broadband band-pass filters having overlapping regions are provided to calculate a magnitude of absorption for each wavelength band for light passing through each broadband band-pass filter, thereby identifying the presence of a gas of interest and the presence of a gas other than the gas of interest.Type: ApplicationFiled: September 8, 2023Publication date: April 11, 2024Inventors: Cheol Woo NAM, Byung Yul MOON, Eung Yul KIM, Jae Hwan KIM, Chun Ho SHIN, Kwang Hun PARK, Myun Gu CHOI, Chang Hwang CHOI, Yong Geol KIM, Jae Min JEON
-
Patent number: 11943490Abstract: The method comprises registering at least one of an internet protocol (IP) address and a media access control (MAC) address of the security devices, generating a plurality of public key and private key pairs, encrypting and storing private keys comprised in the plurality of public key and private key pairs using a master key provided from a master key management unit, selecting any one of a plurality of public key and private key pairs when the access of the security device is approved and providing a certificate comprising the selected public key to the security device, receiving a symmetric key encrypted with the public key of the certificate from the security device, and decrypting the private key using the master key provided from the master key management unit.Type: GrantFiled: January 11, 2022Date of Patent: March 26, 2024Assignee: DUDU Information Technologies, Inc.Inventors: Young Sun Park, Su Man Nam, Jin Woo Lee, Jun Geol Kim, Yun Seong Kim, Yoon Jeong Kim
-
Patent number: 11894346Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: March 10, 2023Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
-
Patent number: 11848274Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.Type: GrantFiled: July 8, 2022Date of Patent: December 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geol Nam, Gunho Chang
-
Patent number: 11705430Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.Type: GrantFiled: February 24, 2021Date of Patent: July 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehyeong Kim, Young Lyong Kim, Geol Nam
-
Publication number: 20230207533Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: March 10, 2023Publication date: June 29, 2023Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
-
Patent number: 11664352Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: May 24, 2021Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
-
Publication number: 20220344271Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Geol Nam, Gunho Chang
-
Patent number: 11462479Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.Type: GrantFiled: August 22, 2019Date of Patent: October 4, 2022Inventors: Geol Nam, Young Lyong Kim
-
Publication number: 20220246582Abstract: Disclosed is a semiconductor package comprising a lower semiconductor chip and upper semiconductor chips vertically stacked on a top surface of the lower semiconductor chip. The upper semiconductor chips include first upper semiconductor chips and a second upper semiconductor chip. The first upper semiconductor chips are between the lower semiconductor chip and the second upper semiconductor chip. A thickness of each of the first upper semiconductor chips is 0.4 to 0.95 times that of the lower semiconductor chip. A thickness of the second upper semiconductor chip is the same as or greater than that of the first upper semiconductor chip. A total number of the first and second upper semiconductor chips is 4n, wherein n is a natural number equal to or greater than three.Type: ApplicationFiled: October 6, 2021Publication date: August 4, 2022Inventors: GEOL NAM, GUNHO CHANG, CHUL-YONG JANG, Dongjoo CHOI
-
Patent number: 11393764Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.Type: GrantFiled: August 14, 2020Date of Patent: July 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geol Nam, Gunho Chang
-
Publication number: 20210280564Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
-
Publication number: 20210183821Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehyeong KIM, Young Lyong KIM, Geol NAM
-
Publication number: 20210159178Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.Type: ApplicationFiled: August 14, 2020Publication date: May 27, 2021Inventors: Geol NAM, Gunho CHANG
-
Patent number: 11018115Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: March 19, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
-
Patent number: 10964670Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.Type: GrantFiled: December 19, 2018Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehyeong Kim, Young Lyong Kim, Geol Nam
-
Publication number: 20200219853Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
-
Patent number: 10651154Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.Type: GrantFiled: July 26, 2018Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Sick Park, Geol Nam, Tae Hong Min, Jihwan Hwang
-
Patent number: 10622335Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of tire plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam