Patents by Inventor Geon KO

Geon KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250158613
    Abstract: An electronic device includes a control signal generation circuit configured to generate a stress enable signal to enter a stress process and a measurement enable signal to enter a measurement process based on a voltage control signal and configured to generate a cycle signal enable signal for generating a cycle signal, and a cycle signal generation circuit configured to apply stress to a plurality of transistors by supplying the plurality of transistors with a source voltage and a ground voltage when the stress enable signal is activated during the stress process, configured to connect current paths of the plurality of transistors to which the stress is applied when the measurement enable signal is activated during the measurement process, and configured to generate the cycle signal that is cyclically toggled when the cycle signal enable signal is activated.
    Type: Application
    Filed: March 28, 2024
    Publication date: May 15, 2025
    Applicant: SK hynix Inc.
    Inventors: Dae Joon KIM, Geon KO, Min Cheol KIM, Hyun Jun PARK
  • Publication number: 20250078908
    Abstract: An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 6, 2025
    Inventors: Geon KO, Choung Ki SONG
  • Publication number: 20240340023
    Abstract: Disclosed are a sigma-delta modulator that directly converts a current signal into digital data, an ADC utilizing the sigma-delta modulator, and a neural network computing system utilizing the ADC. The sigma-delta modulator includes: a delta circuit to generate a differential current between an analog current signal output from a resistive memory and a first current included in the analog current signal, the first current having an amount of current determined by a digital modulation signal; an integration circuit to generate an integration current by integrating the differential current; and a quantization circuit to generate the digital modulation signal corresponding to the integration current. The sigma-delta modulator can minimize the generation of noise by using no capacitor that performs a function by a switch, and can increase a signal processing speed for conversion by allowing the signal processing speed to be determined by a signal processing speed of one element.
    Type: Application
    Filed: November 9, 2023
    Publication date: October 10, 2024
    Inventors: Seung Tak RYU, Chang Yeop LEE, Jun Ho CHEON, Woo Yeong CHO, GEON KO
  • Patent number: 11107511
    Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Woong Choi, Geon Ko
  • Publication number: 20200402552
    Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Applicant: Korea University Research and Business Foundation
    Inventors: Jongsun PARK, Woong CHOI, Geon KO