Patents by Inventor George Steiner

George Steiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240328634
    Abstract: A device to direct the warm air exiting from a Baseboard Heater further away from it laterally in order to avoid the warm air rising behind a curtain that is hanging above the Baseboard Heater.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 3, 2024
    Inventor: George Steiner
  • Publication number: 20240275363
    Abstract: Aspects and embodiments disclosed herein include an acoustic wave device comprising a substrate, a pair of inter-digital transducer (IDT) electrodes formed on the substrate, each of the pair of IDT electrodes including a bus bar and a plurality of fingers extending from the bus bar, fingers of one IDT electrode arranged interleaved with fingers of the other IDT electrode, each of the bus bars of the pair of IDT electrodes having a slotted portion configured on an upper surface of the bus bars opposite to a lower surface contacting the substrate such that at least one hollow within each of the bus bars is opened at least at the upper surface of each of the bus bars, and a dielectric film covering the pair of IDT electrodes, at least a portion of the dielectric film filling in the at least one hollow of each of the bus bars.
    Type: Application
    Filed: January 30, 2024
    Publication date: August 15, 2024
    Inventors: Kurt George Steiner, Alan Sangone Chen, Yosuke Hamaoka, Benjamin Paul Abbott
  • Publication number: 20240258994
    Abstract: An acoustic wave device is disclosed. The acoustic wave device can include a piezoelectric layer, and an interdigital transducer electrode formed with the piezoelectric layer. The interdigital transducer electrode includes a first layer, a second layer over the first layer, and a seed layer between the first layer and the piezoelectric layer. A combination of the first layer and the seed layer has a resistivity that is lower than a resistivity of the first layer alone.
    Type: Application
    Filed: January 30, 2024
    Publication date: August 1, 2024
    Inventors: Kurt George Steiner, Alan Sangone Chen, Yosuke Hamaoka, Benjamin Paul Abbott, Michael David Hill, Kezia Cheng
  • Publication number: 20240140138
    Abstract: An automobile wheel lifting device for the installation of wheels when automobile is on a hydraulic lift. A motorized scissor lift table holds the wheel in a stable vertical position while lifting. Vertically stable position is ensured by a stabilizing arm placed on the wheel by the mechanic with one hand only, before lifting begins. Rate of lifting is such that when the wheel mounting holes are aligned with the studs the lifting can be stopped, the wheel rotated and installed. Lifting device avoids contact with the automobile body by lifting as if the mechanic lifted by hand. Stabilizing arm does not obstruct the view of the mechanic during lifting.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventor: George Steiner
  • Patent number: 8354966
    Abstract: A computer peripheral telecommunications device having an electronic interface for connection to a computer and being configured for adding wireless telecommunication functionality to the computer, the device comprising a movable cover portion for covering the electronic interface while not in use and an antenna integrated in the movable cover portion.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 15, 2013
    Assignee: Option
    Inventors: Peter Delmotte, Sheng-Gen Pan, Roger Laurisch, Georg Steiner, Walter Nijs
  • Patent number: 7776980
    Abstract: Monocyclopentadienyl complexes in which the cyclopentadienyl system bears at least one bridged keto, thioketo, imino or phosphino group, a catalyst system comprising at least one of the monocyclopentadienyl complexes and a process for preparing polyolefins by polymerization or copolymerization of olefins in the presence of the catalyst system.
    Type: Grant
    Filed: March 18, 2006
    Date of Patent: August 17, 2010
    Assignee: Basell Polyolefine GmbH
    Inventors: Shahram Mihan, Benno Bildstein, Georg Steiner
  • Patent number: 7678639
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: March 16, 2010
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 7566964
    Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 28, 2009
    Assignee: Agere Systems Inc.
    Inventors: Seung H. Kang, Roland P. Krebs, Kurt George Steiner, Michael C. Ayukawa, Sailesh Mansinh Merchant
  • Publication number: 20090158062
    Abstract: A computer peripheral telecommunications device having an electronic interface for connection to a computer and being configured for adding wireless telecommunication functionality to the computer, the device comprising a movable cover portion for covering the electronic interface while not in use and an antenna integrated in the movable cover portion.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Applicant: OPTION
    Inventors: Peter Delmotte, Sheng-Gen Pan, Roger Laurisch, Georg Steiner, Walter Nijs
  • Patent number: 7541238
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: June 2, 2009
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Publication number: 20090100668
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Application
    Filed: December 22, 2008
    Publication date: April 23, 2009
    Applicant: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Publication number: 20090018292
    Abstract: Monocyclopentadienyl complexes in which the cyclopentadienyl system bears at least one bridged keto, thioketo, imino or phosphino group, a catalyst system comprising at least one of the monocyclopentadienyl complexes and a process for preparing polyolefins by polymerization or copolymerization of olefins in the presence of the catalyst system.
    Type: Application
    Filed: March 18, 2006
    Publication date: January 15, 2009
    Applicant: Basell Polyolefine GmbH
    Inventors: Shahram Mihan, Benno Bildstein, Georg Steiner
  • Patent number: 7332775
    Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: February 19, 2008
    Assignee: Agere Systems Inc.
    Inventors: Kurt George Steiner, Gerald W. Gibson, Jr., Eduardo Jose Quinones
  • Patent number: 7126198
    Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: October 24, 2006
    Assignee: Agere Systems Inc.
    Inventors: Kurt George Steiner, Gerald W. Gibson, Jr., Eduardo Jose Quinones
  • Patent number: 7067419
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: June 27, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt George Steiner, Joseph Ashley Taylor
  • Patent number: 7068139
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 6960836
    Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 1, 2005
    Assignee: Agere Systems, Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant, John William Osenbach, Kurt George Steiner
  • Patent number: 6879046
    Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: April 12, 2005
    Assignee: Agere Systems Inc.
    Inventors: Gerald W Gibson, Jr., Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 6869873
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Agere Systems Inc.
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Publication number: 20040201101
    Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.
    Type: Application
    Filed: September 30, 2003
    Publication date: October 14, 2004
    Inventors: Seung H. Kang, Roland P. Krebs, Kurt George Steiner, Michael C. Ayukawa, Sailesh Mansinh Merchant