Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.

Abstract: An integrated circuit arrangement comprises at least one one-time programmable storage element, which can be electrically deactivated, having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire.

Abstract: Performance Test Board for connecting at least one device under test (DUT) to a test system which has internal power supply sources (IPS) wherein said Performance Test Board (PTB) comprises at least one DC-DC-converter having an input terminal to which several internal power supply sources of said test system are connected in parallel, an output terminal to which a power supply terminal of said device under test (DUT) is connected and a control terminal to which a further internal power supply source of said test system is connected.

Abstract: The invention involves a process for heating a semi-conductor component, as well as a semi-conductor component, whereby a device for heating the semi-conductor component is provided on the semi-conductor component.

Abstract: An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor.

Abstract: A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.

Abstract: Performance Test Board for connecting at least one device under test (DUT) to a test system which has internal power supply sources (IPS) wherein said Performance Test Board (PTB) comprises at least one DC-DC-converter having an input terminal to which several internal power supply sources of said test system are connected in parallel, an output terminal to which a power supply terminal of said device under test (DUT) is connected and a control terminal to which a further internal power supply source of said test system is connected.

Abstract: A semiconductor product includes a first semiconductor circuit and at least one further integrated semiconductor circuit arranged together on a semiconductor substrate. The first semiconductor circuit and the at least one further semiconductor circuit are separated from one another by a frame region and each including contact connections. Interconnects cross the frame region and short-circuit a contact connection of the first semiconductor circuit with a contact connection of the at least one further semiconductor circuit.

Abstract: The invention involves a process for heating a semi-conductor component, as well as a semi-conductor component, whereby a device for heating the semi-conductor component is provided on the semi-conductor component.

Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Abstract: An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Abstract: The invention relates to a method and a device (1, 11, 21) for detecting the overheating of a semiconductor device, comprising a temperature measuring means (3, 13, 23) that changes its electrical conductivity when the temperature of the semiconductor device changes.

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Abstract: The invention relates to a process for generating a synchronizer pulse, in particular a clock pulse, as well as a synchronizer signal generator device, which is connected to an electronic system, and which emits a synchronizer signal of a particular frequency, which is transferred to at least one device of the electronic system, whereby at least one device is provided with its impedance selected so that a resonance oscillatory circuit—of which the resonance essentially coincides with the frequency of the synchronizer signal—is created for the synchronizer signal generator device.